Cortex-a8 s5pc100 interrupt mechanism

Author: Zhao Xiaoqiang,Hua Qing vision embedded training center lecturer.

1. Overview of vector interrupt

S5pc100 integrates three vector interrupt controllers (represented by Vic later), which use the pl192 core of Arm Based on primecell technology and three tzic, that is, for the interrupt controller involved in the trustzone technology (which is expressed by tzic later), its core is sp890.

94 interrupt sources are supported in s5pc100, where tzic is a trustzone separately designed with a security software interrupt interface, it provides nfiq interruptions Based on Security Control Technology and shields all interruption sources from non-security systems. The following are the features of s5pc100 interrupt controller:

● Support for 94 vector IRQ interruptions

● Flexible hardware interruption priority

● Programmable Interrupt priority settings

● Support priority shielding on hardware

● Support priority shielding in programming

● Built-in IRQ/FIQ/software interrupt Generator

● Built-in registers for debugging

● Original interrupt Status Register/interrupt source request Status Register

● Supports restricted access to data in privileged Mode

When the s5pc100 receives multiple interrupt requests from the on-chip peripherals and external interrupt request pins, The s5pc100 interrupt controller sends a FIQ or IRQ request to s5pc100 after the arbitration process is interrupted. The interrupt arbitration process relies on the hardware priority logic of the processor. On the processor side, it jumps to the interrupt exception handling routine and runs the exception handling program, in this case, the value of the vicaddress register is the entry address of the (ISR) interrupt handler corresponding to the interrupt source after arbitration.

The task of the s5pc100 interrupt controller is to send an interrupt request to the CPU kernel through IRQ or FIQ when multiple interruptions occur. In fact, at first, there were only FIQ (fast interrupt request) and IRQ (General interrupt request) interruptions in the CPU kernel. When other interrupts were designed by chip manufacturers, by adding an interrupt controller to extend the definition, these interrupts are handled based on the priority of the interrupt, more in line with the requirements of the actual application system to provide multiple interrupt sources, In addition, the vector interrupt controller is more flexible and convenient than the previous interrupt method. It leaves the task of judgment to the hardware, making interrupt programming more concise.

In the entire s5pc100 interrupt vector controller, we can see that all the interrupt sources will first enter the tzic arbitration unit. This unit must be configured to determine whether the interrupt source can be used to reach the vic unit, the default mode is safe, so that all interruptions can be arbitrated and handled directly under Vic.

2. s5pc100 interrupt control

(1) F-bit and I-bit of the Program Status Register.

If the F-bit of the CPSR Program Status Register is set to 1, the CPU will not accept FIQ (fast interrupt request) from the interrupt controller ), if the I-bit of the CPSR Program Status Register is set to 1, the CPU will not accept IRQ (interrupt request) from the interrupt controller ). Therefore, in order to enable FIQ and IRQ, the F and I bits of the CPSR program State register must be cleared first, and the corresponding bits in the interrupt shield register intmsk must also be cleared.

(2) intselect ).

The Cortex-A8 provides two interrupt modes: FIQ mode and IRQ mode. All interrupt sources must determine which interrupt mode to use when interrupting requests.

3. s5pc100 interrupt source Overview

In this chip, there are three VIC units, among which vic0 covers the interrupt source of the system, DMA, and timer. vic1 includes the ARM core, power management, and memory management, the interrupt source of storage management. vic2 contains multimedia, security extension, and other interrupt sources. For more information, see the user manual.

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