Cortex-Mo Instruction Set

The processor uses the ARMv6-M thumb instruction set, including a large number of 32-bit instructions using the thumb-2 technology. Table 7-22 lists the Cortex-M0 instructions and their cycles. The cycle count is based on the system in the Zero Wait state.

Table 7-22 Cortex-M0 instructions and their cycles

Operation	Description	Sort order	Weekly
Move	8-bit immediate	Movs Rd, # <Imm>	1
	Lo to Lo	Movs Rd, RM	1
	Any to any	MoV Rd, RM	1
	Any to PC	MoV PC, RM	3
Add	3-bit immediate	Adds Rd, RN, # <Imm>	1
	All registers Lo	Adds Rd, RN, RM	1

Continue table

Operation	Description	Sort order	Weekly
	Any to any	Add Rd, RD, RM	1
	Any to PC	Add PC, PC, RM	3
	8-bit immediate	Adds Rd, RD, # <Imm>	1
	With carry	ADCs Rd, RD, RM	1
	Immediate to SP	Add SP, SP, # <Imm>	1
	Form address from SP	Add Rd, SP, # <Imm>	1
	Form address from PC	ADR Rd, <label>	1
Subtract	Lo to Lo	Subs Rd, RN, RM	1
	3-bit immediate	Subs Rd, RN, # <Imm>	1
	8-bit immediate	Subs Rd, RD, # <Imm>	1
	With carry	Sbcs Rd, RD, RM	1
	Immediate from SP	Sub sp, SP, # <Imm>	1
	Negate	RSBs Rd, RN, #0	1
Multiply	Multiply	Muls Rd, RM, RD	1 or 32
Compare	Compare	Cmp rn, RM	1
	Negative	Cmp rn, RM	1
	Immediate	Cmp rn, # <Imm>	1
Logical	And	ANDS Rd, RD, RM	1
	Exclusive or	Eors Rd, RD, RM	1
	Or	Orrs Rd, RD, RM	1
	Bit clear	BICS Rd, RD, RM	1
	Move not	Mvns Rd, RM	1
	And Test	Tst RN, RM	1
Shift	Logical shift left by immediate	Lsls Rd, RM, # <shift>	1
	Logical shift left by register	Lsls Rd, RD, RS	1
	Logical shift right by immediate	Lsrs Rd, RM, # <shift>	1
	Logical shift right by register	Lsrs Rd, RD, RS	1
	Arithmetic shift right	ASRs Rd, RM, # <shift>	1
	Arithmetic shift right by register	ASRs Rd, RD, RS	1
Rotate	Rotate right by register	RORs Rd, RD, RS	1
Load	Word, immediate offset	LDR Rd, [Rn, # <Imm>]	2
	Halfword, immediate offset	Ldrh Rd, [Rn, # <Imm>]	2
	Byte, immediate offset	Ldrb Rd, [Rn, # <Imm>]	2
	Word, register offset	LDR Rd, [Rn, RM]	2

Continue table

Operation	Description	Sort order	Weekly
	Halfword, register offset	Ldrh Rd, [Rn, RM]	2
	Signed halfword, register offset	Ldrsh Rd, [Rn, RM]	2
	Byte, register offset	Ldrb Rd, [Rn, RM]	2
	Signed byte, register offset	Ldrsb Rd, [Rn, RM]	2
	PC-relative	LDR Rd, <label>	2
	SP-relative	LDR Rd, [Sp, # <Imm>]	2
	Multiple, excluding Base	LDM rn !, {<Loreglist>}	1 + n
	Multiple, including base	Ldm rn, {<loreglist>}	1 + n
Store	Word, immediate offset	STR Rd, [Rn, # <Imm>]	2
	Halfword, immediate offset	Strh Rd, [Rn, # <Imm>]	2
	Byte, immediate offset	Strb Rd, [Rn, # <Imm>]	2
	Word, register offset	STR Rd, [Rn, RM]	2
	Halfword, register offset	Strh Rd, [Rn, RM]	2
	Byte, register offset	Strb Rd, [Rn, RM]	2
	SP-relative	STR Rd, [Sp, # <Imm>]	2
	Multiple	STM rn !, {<Loreglist>}	1 + n
Push	Push	Push {<loreglist>}	1 + n
	Push with Link register	Push {<loreglist>, LR}	1 + n
Pop	Pop	Pop {<loreglist>}	1 + n
	Pop and return	Pop {<loreglist>, PC}	4 + n
Branch	Conditional	B <CC> <label>	1 or 3
	Unconditional	B <label>	3
	With Link	BL <label>	4
	With exchange	BX RM	3
	With link and exchange	Blx RM	3
Extend	Signed halfword to word	Sxth Rd, RM	1
	Signed byte to word	Sxtb Rd, RM	1
	Unsigned halfword	Uxth Rd, RM	1
	Unsigned byte	Uxtb Rd, RM	1
Reverse	Bytes in Word	Rev Rd, RM	1
	Bytes in both halfwords	Rev16 Rd, RM	1
	Signed bottom half word	Revsh Rd, RM	1
State Change	Supervisor call	SVC # <Imm>	-
	Disable interrupts	Cpsid I	1

Operation	Description	Sort order	Weekly
	Enable interrupts	Cpsie I	1
	Read special register	Mrs Rd, <specreg>	4
	Write special register	MSR <specreg>, Rn	4
	Breakpoint	Bkpt # <Imm>	-
Hint	Send event	Sev	1
	Wait for event	WFE	2
	Wait for interrupt	WFI	2
	Yield	Yield	1
Hint	No operation	NOP	1
Barriers	Instruction Synchronization	ISB	4
	Data Memory	DMB	4
	Data Synchronization	DSB	4

The C code of ISO/IEC cannot directly obtain instructions for some Cortex-M0. Table 7-23 lists some internal functions provided by the C compiler of cmsis for generating these commands. If a C compiler does not support proper internal functions, you need to use embedded assembly to obtain related commands.

Table 7-23 Internal cmsis Functions

Orders	Cmsis internal functions	Orders	Cmsis internal functions
Cpsie I	Void _ enable_irq (void)	Rev	Uint32_t _ Rev (uint32_t int value)
Cpsid I	Void _ disable_irq (void)	Rev16	Uint32_t _ rev16 (uint32_t int value)
ISB	Void _ ISB (void)	Revsh	Uint32_t _ revsh (uint32_t int value)
DSB	Void _ DSB (void)	Sev	Void _ sev (void)
DMB	Void _ DMB (void)	WFE	Void _ WFE (void)
NOP	Void _ Nop (void)	WFI	Void _ WFI (void)

Cmsis also provides several functions for obtaining special registers, as shown in table 7-24.

Table 7-24 functions provided by cmsis for obtaining special registers

Special Registers	Obtaining Method	Cmsis Functions
Primask	Read	Uint32_t _ get_primask (void)
	Write	Void _ set_primask (void)
Control	Read	Uint32_t _ get_control (uint32_t value)
	Write	Void _ SET_CONTROL (uint32_t value)
MSP	Read	Uint32_t _ get_msp (void)
	Write	Void _ set_msp (uint32_t topofmainstack)
PSP	Read	Uint32_t _ get_psp (void)
	Write	Void _ set_psp (uint32_t topofmainstack)