Cortex_m3_stm32 Embedded Learning Note (19): DMA Experiment (high-speed transfer)

DMA, all called: direct memory access, i.e. DMA transmission mode without the direct control of the CPU transmission, and no interruption of processing to retain the site and the recovery site process, through the hardware for RAM and I/O equipment to open a direct data transmission path, can make the CPU efficiency greatly improved.

That is, before the DMA transfer, the CPU to the bus control to the DMA controller, and after the end of the DMA transfer, the DMA controller should immediately return the bus control to the CPU. A complete DMA transfer process must go through the following 4 steps. The 1.DMA requests the CPU to initialize the DMA controller and issue an operation command to the I/O interface, which requests a DMA request. The 2.DMA Response DMA controller selects the optimal level and shielding for the DMA request, and presents the bus request to the bus ruling logic. The bus control is freed when the CPU executes the current bus cycle. At this point, the bus decision logic output bus answer, indicating that the DMA has responded, through the DMA controller notifies the I/O interface to start the DMA transfer. After the 3.DMA transmission DMA controller obtains the bus control, the CPU hangs immediately or only performs internal operation, the DMA controller outputs the read-write command, directly controls the RAM and the I/O interface for DMA transmission. 4.DMA end when the required batch data transfer is complete, the DMA controller releases the bus control and sends an end signal to the I/O interface. When the I/O interface receives the end signal, on the one hand stop the work of I/O device, on the other hand interrupt request to the CPU, so that the CPU from the state of non-intervention, and perform a check the DMA transfer operation is correct code. Finally, carry out the original program with the result and status of the operation.

It's simply a way of transmitting data at high speed.

DMA requests from peripherals (timx, ADCs, SPIx, I2CX, and Usartx) are either logically or input to the DMA controller, which means that only one request can be valid at the same time. The DMA request of the peripheral can be turned on or off independently by setting the control bit in the corresponding peripheral register.
Below is a list of the DMA1 channels:

This experiment realizes the DMA transmission of serial port 1, which is used to Channel 4

To configure the DMA general steps:

1) Enable DMA clock
2) initialize DMA Channel 4 parameter
3) Enable serial DMA to send
4) Enable DMA1 Channel 4, start the transmission.

5) Querying DMA transfer status

Configuring DMA.C for DMA

#include "dma.h" Dma_inittypedef dma_initstructure;u16 dma1_mem_len;//Save DMA each channel configuration for each data transfer length//DMA1//The transmission form here is fixed, This should be modified according to different situations//from memory---Peripheral mode/8-bit data width/memory increment mode//DMA_CHX:DMA Channel Chx//cpar: Peripheral address//cmar: Memory address//CNDTR: Data transfer volume void Mydma_ Config (dma_channel_typedef* dma_chx,u32 cpar,u32 cmar,u16 cndtr) {rcc_ahbperiphclockcmd (RCC_AHBPERIPH_DMA1, ENABLE) ;//Enable DMA clock Dma_deinit (DMA_CHX);//Set the DMA Channel 1 register to the default value dma1_mem_len=cndtr;dma_initstructure.dma_peripheralbaseaddr= CPAR;//DMA peripheral serial Port base address DMA_INITSTRUCTURE.DMA_MEMORYBASEADDR=CMAR;//DMA memory base address Dma_initstructure.dma_dir=dma_dir_ peripheraldst;//the size of the DMA cache for the data transfer direction memory to the peripheral DMA_INITSTRUCTURE.DMA_BUFFERSIZE=CNDTR;//DMA channel Dma_initstructure.dma_ peripheralinc=dma_peripheralinc_disable;//peripheral address is not changed dma_initstructure.dma_memoryinc=dma_memoryinc_enable;// Memory address register increment//Data width 8-bit dma_initstructure.dma_peripheraldatasize=dma_peripheraldatasize_byte;//data width 8-bit Dma_ Initstructure.dma_memorydatasize=dma_memorydatasize_byte; dma_initstructure.dma_mode=dma_mode_normal;//working in normal cache mode DMA_INITSTRUCTURE.DMA_PRIORITY=DMA_PRIORITY_MEDIUM;//DM Channel has medium priority dma_initstructure.dma_m2m=dma_m2m_disable;//non-memory to Memory transfer Dma_init (Dma_chx,&dma_ initstructure);//Initialize DMA channel}//to turn on DMA transfer void Mydma_enable (DMA_CHANNEL_TYPEDEF*DMA_CHX) {dma_cmd (dma_chx,disable); /Close the channel Dma_setcurrdatacounter (Dma1_channel4,dma1_mem_len) indicated by USART1 TX DMA1;//Set the size of the DMA cache Dma_cmd (Dma_chx, ENABLE); Enable USART1 the channel indicated by TX DMA1}

Look at this sentence.

void Mydma_config (dma_channel_typedef* dma_chx,u32 cpar,u32 cmar,u16 cndtr)

This is the initialization of the DMA statement, the first parameter to fill the DMA channel CHX, (this experiment is using Channel 4), the second parameter is the peripheral address, we are to send data to the serial port, so to fillThe serial port accepts the address of the sending data memory Usart1->dr, the third parameter fills the memory address, (can be understood as the address of the data to be sent), the fourth parameter fills in the data transfer amount (that is, the size to be sent)

dma.h

#ifndef _dma_h#define _dma_h#include "sys.h" void Mydma_config (dma_channel_typedef* dma_chx,u32 cpar,u32 cmar,u16 CNDTR ); void mydma_enable (DMA_CHANNEL_TYPEDEF*DMA_CHX); #endif

Main function

#include "led.h" #include "delay.h" #include "sys.h" #include "usart.h" #include "lcd.h" #include "key.h" #include "dma.h" Const U8 text_to_send[]={"DMA test~~~~~~"}; #define Text_lenth sizeof (text_to_send) -1u8 sendbuff[(text_lenth+2) *100]; U16 i;u8 t;float pro=0;void init (void) {delay_init (); Uart_init (9600); Led_init (); Key_init (); Lcd_init ();//DMA1 Channel 4, peripheral is serial port 1, memory is Sendbuff, long (text_lenth+2) *100.mydma_config (Dma1_channel4, (u32) &USART1-> DR, (U32) Sendbuff, (text_lenth+2) *100); point_color=red; Lcd_showstring (60,40,200,24,24, "DMA test~^~"); Lcd_showstring (60,70,200,16,16, "M difficult"); Lcd_showstring (60,90,200,16,16, "by--yh"); Lcd_showstring (60,110,200,16,16, "2015/1/25"); Lcd_showstring (60,130,200,16,16, "Key0:start"); T=0;for (i=0;i< (text_lenth+2) *100;i++)//fill buffer (generate pending data) {if (t >=text_lenth)//Add newline {sendbuff[i++]=0x0d; sendbuff[i]=0x0a;t=0;} elsesendbuff[i++]=text_to_send[t++];}} int main (void) {init (); i=0; point_color=blue;//set the font to blue while (1) {t=key_scan (0), if (t==key0_pres) {lcd_showstring (60,150,200,16,16,"Start transimit ..."); Lcd_showstring (60,170,200,16,16, "%");//Display percent printf ("\r\ndma DATA: \ r \ n"); Usart_dmacmd (usart1,usart_dmareq_tx,enable); Mydma_enable (DMA1_CHANNEL4);//Start DMA transfer! Wait for the DMA transfer to complete, at this point we do other things, lighting//actual application, during the transfer of data, you can perform additional tasks while (1) {if (Dma_getflagstatus (DMA1_FLAG_TC4)!=reset)//wait for Channel 4 Transfer Complete {dma_clearflag (DMA1_FLAG_TC4);//Clear Channel 4 transmit complete flag break;} Pro=dma_getcurrdatacounter (DMA1_CHANNEL4);//Current remaining data volume pro=1-pro/((text_lenth+2) *100);//Get percent pro*=100; Enlarged 100 times Times lcd_shownum (60,170,pro,3,16);//led1=! LED1;} Lcd_shownum (60,170,100,3,16);//Display 100% lcd_showstring (60,150,200,16,16, "Transimit finished!"); /Transfer complete}i++;d Elay_ms; if (i==20) {led0=! led0;i=0;}}}

Has a function

uint16_t Dma_getcurrdatacounter (dma_channel_typedef* dmay_channelx)

Get the current amount of data remaining size (how much is not sent out)

In fact, the most important thing when transmitting data is that the MCU CPU can do other things, this is the advantage of using DMA transmission (although this experiment is not reflected)

We can see the following contents in the serial assistant.

It is indicated that the serial port receives the data of DMA transmission.

This experiment can be compared to the previous serial communication experiment, which is the normal sending

Cortex_m3_stm32 Embedded Learning Note (19): DMA Experiment (high-speed transfer)