COTEX-M3 Core LPC17XX Series clock and its configuration method

First, background:

Recently, a project has been taken over, the core chip is both the LPC17XX series MCU, core arm of the COTEX-M3 core.

If you want to play with an MCU, you have to take care of its clock!

The clock is to the MCU, like the human heart. It gives the AHB, APB Bus The blood (clock frequency), and the devices that hang on the AHB (Advance High bus) bus are like our various organs, the peripherals that hang on the APB (Adance peripheral bus) are like human limbs. Each organ and limb can function only when your blood (clock frequency) is properly supplied.

This article is to introduce and summarize the clock structure and configuration method of Lpc17xx series.

Second, the text:

Apart, first on a lpc17xx clock.

As shown in the figure, the MCU's original clock power comes from one of three places,

Osc_clk--> by the external "XTAL1", "XTAL2" crystal oscillator to provide a clock source;

Rtc_clk--> by the external "RTCX1", "RTCX2" crystal oscillator to provide a clock source;

The irc_osc--> is provided by a crystal oscillator inside the MCU to provide a clock source.

The three clocks provide clocks to the main PLL (PLL0), PLL1, and watchdog respectively. ，

The clock supplied to the CPU is provided by either the main PLL (PLL0) or directly from one of the three crystal oscillator sources;

The clock supplied with the USB is provided by the main PLL (PLL0) or PLL1;

The clock supplied to the watchdog is provided by the "RTC_CLK" or "Irc_osc" clock.

Now it's time to say how to configure the clock:

1. Configure CPU Clock (CCLK):

CPU Clock CCLK If provided by the PLL0, then PLL0 will supply its clock to rise frequency, after the rise frequency, then reduce frequency for CPU use, that is, CCLK, as to why the first rise frequency and then reduce frequency, temporarily unknown,

Maybe it's just the PLL work mechanism. The following is a specific procedure for configuring the CPU Clock (CCLK):

A, describe the main oscillator-that is, the main oscillator size range, there is no stability, etc., the configured register is "SCS".

B. Configure peripheral Clocks:

Be careful here! Follow the normal thought sequence, "B" This step should be after all steps, but the LPC17XX series of MCU rules, before the Enable PLL0, the peripheral clock configuration to complete the first,

Therefore, configure the peripheral clock first.

So, what is a peripheral clock?

After the PLL0 is lowered, a CCLK clock is generated for use by the CPU. The CCLK is again divided for use by all peripherals.

The peripheral clock is configured to configure the clock size of each peripheral (that is, to cclk a few frequencies).

Each series CCLK has its maximum operating frequency, whichever is greater than the maximum operating frequency, and the configured frequency reduction (crossover) size register is "Cclkcfg".

Configure peripheral clock registers as "PCLKSEL0/1"

Before configuring the peripheral clock, consider how much the PPL0 is going to reduce the frequency to get the desired CCLK value, which is actually considered in the "D" step, so the logic here is a bit messy.

During the reading process, you can skip this step, look directly at the "C" step, and finally jump back to see the "B" step, but the actual operation must follow this step.

C, from the three oscillator select the clock supply PLL0, the configuration of the register is "Clksrcsel".

D, configure the "pll0cfg" register, to set the PLL0 rise and decrease the frequency value of the size, register as follows:

M is the multiplier value, n is the frequency division value, when using the crystal source as "Rtc_clk", the M-value is referred to table 4.8 recommended values.

PLL0 calculation methods such as:

　　　　

When calculating PLL0, the meanings of the parameters of each calculated variable are as follows:

　　　　

E, finally enable the PLL0 clock and select whether to choose PLL0 as the input clock CCLK, the operation of the register is "Pll0con"

F, for example: MCU external crystal oscillator 12MHZ, I need the CPU to work in the frequency of 100MHZ. So according to the equation, M = +, N = 6.

Fcco = (2 * 12MHZ)/6 =400mhz. Then 4 divides, finally obtains the CCLK to be 100MHZ.

The configuration code is as follows:

　　

#if(Pll0_setup)LPC_SC->pll0cfg =Pll0cfg_val; LPC_SC->pll0con =0x01;/*PLL0 Enable*/LPC_SC->pll0feed =0xAA; LPC_SC->pll0feed =0x55;  while(! (Lpc_sc->pll0stat & (1<< -)));/*Wait for PLOCK0*/LPC_SC->pll0con =0x03;/*PLL0 Enable & Connect*/LPC_SC->pll0feed =0xAA; LPC_SC->pll0feed =0x55;#endif

2, the configuration of USB clock:

such as the overall clock diagram, the USB clock can only be provided by PLL0 or PLL1, and! If the USB clock is provided by PLL0, then the PLL0 clock source must be an external crystal oscillator!

USB requires a 48MHZ clock source with a duty ratio of 50%, which means that the PLL1 or PLL0 clock Fcco must be an even number of 48MHZ to provide the appropriate clock for the USB.

A, if provided by PLL0, then the "1" step is configured to complete the PLL0, through the USB divider to get the USB clock to meet the conditions.

For example: The CLK requirement for USB is 48MZH, then the PLL0 frequency is configured for an even number of 48MHZ, then the frequency divider via the USB clock to obtain the required clock.

B, if provided by PLL1, then you have to say how PLL1 is configured:

A, PLL1 only support clock input from 10MHZ to 25MHZ, and can only be external clock source, so clock source is not selected;

B, set PLL1 "M" Value and "P value", PLL1 similar to PLL0, there will be a first rise frequency after the process of reducing frequency, but you can see that PLL1 is a special USB clock source,

So the limit for each value will be more.

PLL1 formula for output frequency:

　　

The Fcco frequency can be calculated according to the following formula:

　　

Summarize:

The frequency range of the Fosc (clock source) must be 10mhz~25mhz,

The USBCLK must be 48MHZ,

The range of Fcco is: 156mhz~320mhz;

As an example:

The external crystal oscillator of the input is 12MHZ, the value of the configuration "M" is 4, the value of "P" is 2, calculated by the formula can be obtained by the PLL1 up to 192MHZ, and then divide to 48MHZ to provide USB use.

The PLL1 configuration code is as follows:

#if(Pll1_setup)LPC_SC->pll1cfg =Pll1cfg_val; LPC_SC->pll1con =0x01;/*PLL1 Enable*/LPC_SC->pll1feed =0xAA; LPC_SC->pll1feed =0x55;  while(! (Lpc_sc->pll1stat & (1<<Ten)));/*Wait for PLOCK1*/LPC_SC->pll1con =0x03;/*PLL1 Enable & Connect*/LPC_SC->pll1feed =0xAA; LPC_SC->pll1feed =0x55;#elseLPC_SC->usbclkcfg = Usbclkcfg_val;/*Setup USB Clock Divider*/#endif

3, the watchdog WD_CLK has not been used, the next time to match, then do record.

Three, Summary:

Whether it is the LPC17XX series of the COTEX-M3 core, the STM32 series, or the higher-order ARM9,ARM11, the clock is the best starting point to explore them.

For practical use, the use of MCUs is both the use of various peripherals, or the realization of a variety of communications. No matter what peripherals, UART, IIC, CAN, USB, etc.,

The key to working correctly is to give the correct clock. The clock selection method uses the clock graph on the MCU Chip handbook to reverse back, first to determine the peripheral clock according to the needs of the peripheral,

Then consider the CPU clock and then reverse the selection to the original clock source.

Finished, make a record here for the next reference.

Record location: Shenzhen wz

Record time: June 3, 2016

COTEX-M3 Core LPC17XX Series clock and its configuration method