Counters of FPGA design skills

Recently, according to the RF system, in order to save FPGA's internal logical resources and pin optimization, we have recorded some of my occasional records based on the characteristics of the counter.

1. Clock frequency division

In projects, clock frequency division is often required, except for the use of PLL or DLL. Sometimes there are many frequency division clocks, and too many PLL or DLL is not suitable, using Counters is a good solution.

The following describes how to generate 1 kHz pulse and 1Hz clock signal by 50 MHz clock division. To avoid clock offset (Skew), the master clock must be used as the cycle when clock frequency division is designed.

//////////////////////////////////////// //////////////////

/*************** 50000 = 500*100 ***************** *****/

Always @ (posedge clk_50m) begin

If (! Rst_n | cnt100 = 7'd100) cnt100 <= 7'd0;

Else cnt100 <= cnt100 + 7'd1;

End

 

Always @ (posedge clk_50m) begin

If (! Rst_n | cnt500 = 10'd500) cnt500 <= 10' D0;

Else if (cnt100 = 7'd100) cnt500 <= cnt500 + 10' D1;

Else cnt500 <= cnt500;

End

 

Always @ (posedge clk_50m) begin

If (cnt500 = 10'd500) clk_1k <= 1;

Else clk_1k <= 0;

End

//////////////////////////////////////// //////////////////

/************ 50000000 = 500*100*1000 ******************/

Always @ (posedge clk_50m) begin

If (! Rst_n | cnt1k = 10 'd499) cnt1k <= 10' D0;

Else if (clk_1k) cnt1k <= cnt1k + 10'd1;

Else cnt1k <= cnt1k;

End

 

Always @ (posedge clk_50m) begin

If (! Rst_n) clk_1hz <= 0;

Else if (cnt1k = 10 'd249 & clk_1k) clk_1hz <= ~ Clk_1hz;

Else clk_1hz <= clk_1hz;

End

 

2. Data Path Selection

In some system designs, you often need to select a data path and determine its validity. The following describes how to use a four-digit counter.

Reg [3: 0] CNT;

// 0000 0001 0010 0011 0100 0101 0110 0111 ......

Always @ (posedge CLK) begin

If (! Rst_n) CNT <= 4'd1;

Else CNT <= CNT + 4'd1;

End

2.1 data path model

Shows the 4-channel data path model. Figure 1 data path model

2.2 valid data paths

2.2.1 The data path is valid after two clocks

Assign datadv = CNT [0];

Assign datapath = CNT [2:1];

Simulation 2.

Figure 2 simulation of two clock cycles through the data path

2.2.2 the data path is valid after four clock periods

Assign datadv = CNT [1] & CNT [0];

Assign datapath = CNT [3: 2];

Simulation 3 shows.

Figure 3 Simulation of four clock cycles through data channels

Counters of FPGA design skills