CPU explanation 8: introduction of DMA Controller

In other words, the main task of the CPU is to read the program instruction stream for execution. The instruction mainly consists of two parts: calculation, self-processing, and control of data transmission between devices, this is done by interacting with the Device Manager or device adapter. It is nothing more than reading and writing the registers of the device controller.

Even the registers of the read/write device controller do not have their own experience. They only send the address or add data to the bus, and some routes pass through the middle to the device controller. This further reduces the CPU complexity. In this case, the CPU work is not complicated. It seems that the workload is light enough. Do you still need to reduce it, or is it possible to reduce it?

The answer is yes. Go back to CPU 3: read/write hard disk instructions. The CPU wants to read data from the hard disk, and the smallest data unit of the hard disk is one sector, that is, 512 bytes. In PIO reading mode, the CPU and the disk controller can only read two bytes of data from the disk controller at a time. In this way, the command is executed cyclically until the entire sector is read.

The first day, there is no problem with this process. However, the user experience is poor. Because of disk reading data, data transmission on the I/O bus is also slow, and the CPU reads two bytes of content each time for transmission, most of the time is actually waiting, and at this time the CPU is not able to do anything else, it is a waste of CPU resources.

Is there a good solution? Someone really thought of a wonderful solution. Because the data exchange between devices does not require CPU data. Their control is nothing more than notifying them to prepare and send data and to receive data. This notification is nothing more than sending and receiving signals to the bus, the CPU can submit the task to a third-party device. Of course, this device is called a DMA controller. The CPU first interacts with the DMA controller, telling him which two devices are responsible for data interaction, and then notifying the CPU when the interaction is complete. In this way, if the program wants to read hard disk data, it does not need to use insw to interact with the disk controller in one word. Instead, it only needs to tell the DMA controller, I want to read the hard disk sectors to the memory location, and the CPU can do some other work when the DMA controls data interaction.
In this way, the CPU usage is greatly reduced, and program control is much more convenient.

Therefore, the proposal of the DMA controller idea must be unanimously recognized by everyone. Therefore, everyone sat down to set a DMA specification so that various devices can support this DMA transmission mode, some DMA content will be added to our ide interface specifications. Naturally, our IDE Hard Disk can use DMA to read and write data. This reading process involves another step. The program controls the CPU, the CPU controls the DMA controller, the DMA controller controls the disk controller, and the disk controller controls our IDE hard disk. Is there a taste of the software design model?