CPU Interface Register

1,CPU Interface control Register, GICC_CTLR: Controls the Register, controls whether to escalate interrupts to the processor;

2. Interrupt First Mask Register, GICC_PMR: Interrupt priority Masking Register, we can understand that the processor is not the average person, not everyone can disturb, this register is to set a priority threshold value, Interrupts that have precedence above this value are escalated to the processor response;

3. Interrupt Acknowledge Register, Gicc_iar: Interrupt response Register, the processor reads this register to obtain the reported interrupt number; Reading this action can be considered as a response to the interrupt;

4. End of Interrupt Register, Gicc_eoir: The processor writes this register to inform the CPU interface that the interrupt has been processed

5. Running Priority Register, GICC_RPR: Runs the precedence register, and the value of this register represents the running priority of the current CPU interface

6. highest priority Pending Interrupt Register, Gicc_hppir: The highest precedence interrupt number for the current Pending state, when the interrupt preemption is allowed, If the priority value of this interrupt is greater than the value of the run-priority register, an interrupt preemption occurs;

7. CPU Interface Identification Register, GICC_IIDR:CPU Interface Identity Register, this register provides some information of CPU Interface, including product good, schema version, etc.;

CPU Interface Register