CPU memory management mode and addressing

 

 

 

The 32-bit cpu address bus is extended to 32-bit, which is consistent with the data bus width. Therefore, you do not need to use the address expression "physical address = segment: Offset" on a 32-bit server. It turns out that each segment specified in a 16-bit server is not larger than 64 kB in a 32-bit server. Therefore, for a 32-bit server, the simplest method is to use a 32-bit host to identify the storage address of a single byte. when addressing a 32-bit host, the address can be directly found. This address storage model belongs to the "flat storage model ".

However, new products generally want to follow the principle of "backward compatibility. Therefore, the 16-bit addressing mode is fully reserved for 32-bit machines. That is, the addressing capacity is 1 M, and the segmentation mechanism; each segment cannot exceed 64 KB. This is what we usually call the "real mode ". The address storage model belongs to the "real address storage model ".

Secondly, considering that the program is usually a functional module, although segmentation is not necessary, segmentation can greatly improve the programmer's efficiency in program management. Therefore, 32-bit hosts also adopt the segment + offset mode for addressing. However, unlike the actual model, because the address line and data line width are consistent, each segment can reach a maximum of 4 GB, and the segment base address is also 32-bit without the need to move left. In the address storage model, this is a block address storage model ". However, in 32-bit machines, although the general registers and Mark registers are all extended to 32-bit, the segment registers are still 16-bit (why not change them ?? I guess this is easier for backward compatibility ). Therefore, in 32-bit addressing, the segment register is no longer a segment base address (the number of digits is not enough) but a Selection Sub-address. This selection sub-corresponds to a 64-bit long descriptor, and 32-bit in the 64-bit descriptor is the base address of the segment. So we can find the segment base address in one step through the segment register on a 16-bit server, but now we have two steps in the 32-bit server: First find and select the child, and then find the Segment Base Address by selecting the child. The base address of the segment is found, and the offset address is added to the physical address. As you can see, the addressing of the 32-bit block mode is clearly described. In fact, the first story is far from complete.

In the process described above, it is easy to find that two problems are not explained. (1) How does the CPU match the Selection Sub-Descriptor? (2) Since it is a 64-bit Descriptor and 32 bits are used to represent the base address, what are the remaining 32 bits used? In addition, with the development of 32-bit machines, the operating system has also made great strides, and DOS in single-task mode has been replaced by windows in multi-task mode. That is to say, the current resident in the memory is often more than one program, but it is likely that multiple programs are in the memory at the same time. Now there is no limit on the segment size, and programs are likely to compete for addresses. If the core program is destroyed, the computer will crash. This is like driving a car on the road. If there is only one car to drive, how can we drive it? But if there is no additional traffic rule, the car will snatch the road, the road will be paralyzed. Therefore, in the case of multiple tasks, a "traffic rule" must be developed for addressing to ensure the orderly work of the multi-task system. What kind of rules are formulated? First of all, since the program preemptible the addresses of other programs unconsciously, if the addressing contains a query process, it can effectively avoid address grabbing. That is to say, first ask if the address is occupied by a program segment? In addition to telling the CPU's base address, the program segment with occupied addresses should also tell the CPU's own length information. In this way, other program segments can be easily queried. Second, multi-task addressing should preferably include content with a higher priority and give way to the core program in an emergency. This is like on the road. Generally, the vehicle gets out of the road according to the rules. However, when a police car or ambulance executes a task, it can give priority to other vehicles. Therefore, a priority should also be defined. Then, the program segment occupying the address tells the CPU priority. In general, the concept of a simple "segment" on a 16-bit server is now complicated. For example, in the process of growing up with one person, the thinking at the beginning is always naive, and the corresponding thinking can only solve simple problems. Only when your thinking gets rid of childishness, can solve more complex things. Now the CPU is free from the naive 16-bit. It should not be as superficial as it is when describing "segments. On a 32-bit server, "segment" has three elements: base address, length, and attribute (the attribute contains priority and other content ). To make a complete reference or give the three elements at a time, a new data structure needs to be defined. This structure is the descriptor mentioned above. Each descriptor occupies 64-bit and has enough length to contain three elements of the segment. Of course, there are more than one program in the memory and more than one segment in the program, so there is not one descriptor, but many. The simplest management method is to put all the descriptors in a continuous bucket, and then route the sequence numbers to each descriptor. To find a specific descriptor, you only need to find this contiguous bucket and then give the sequence number. These centralized descriptors form a table, which is usually called a descriptor table. Therefore, to find the information of a segment, you must first find the descriptor table. That is to say, to find a specific descriptor, you must first know the base address of the descriptor table. In a 32-bit cpu, a 48-bit special register is used to store information about the Global Descriptor Table. This register is called GDTR. The base address of the Global Descriptor Table is given for 32 bits in height, and the limit on the length of the descriptor table is given for 16 bits in height. Therefore, a Global Descriptor Table can be up to 64 KB. Then, up to 64 KB/8b = 8 K descriptors can be put. So if you want to select any descriptor in it, you can use 13 BITs. In a 32-bit cpu, the 16-bit register's 13-bit high is used to store the serial number of a specific descriptor. In fact, the function of the segment register is to select the descriptor. Because of this, the segment register is usually called a selector. After a lengthy introduction, the 32-bit segment addressing process has largely vanished: Find the serial number in the segment register and find the base address of the Global Descriptor Table in GDTR, then you can find the target descriptor. Then, extract the base address of the segment from the descriptor and add the offset address to obtain the "physical address" of the segment ".

This addressing process provides a powerful guarantee for multi-task execution. It can be imagined that this is a leap in computer execution performance! Since then, the high-speed cpu will no longer be useless. It can take advantage of its own speed to the maximum extent and process many tasks at the same time. Yes, we have reason to be excited when we see a new scene. However, we should not meet this requirement. We should follow the new world to give us a glimmer of light, continue to move forward, to find this new world. People keep making things more perfect in this way. At this point, our understanding of the addressing process is just a start, but this is a good start, we have realized the powerful advantages of 32-bit cpu. This is enough to make us look forward to the complete 32-bit CPU addressing. Let's boost our morale and move on with our predecessors!

We know that program code and data can run only when they reside in the memory. However, the number of system memory is very limited and it often cannot accommodate all the code and data of a complete program, what's more, it is now a multi-task system, and it is obviously unlikely that the memory will reside in all task programs. The old-fashioned system splits the program into small portions, leaving only the portion needed to run the current system in the memory and the rest in the hard disk. After the system finishes processing the current task segment, it transfers the next task segment from the external storage, and this task is completed by the programmer. Obviously, this increases the burden on programmers.
A virtual memory technology is developed for multitasking systems. The virtual memory technology is an on-demand dynamic memory allocation method taken over by the operating system, it allows the program to unconsciously use a storage space larger than the actual physical space (in fact, the storage space required by the program is stored in the physical memory and disk in the form of pages ). The Virtual Memory combines the system hard disk space with the actual system memory for the process to use, providing a much larger virtual space for the process than the memory. When the program runs, a small part of the virtual address space is mapped to the memory, and the rest are stored on the hard disk (that is, the virtual space of the program is equal to the actual physical memory and part of the hard disk space ). When the accessed virtual address is not in the memory, it indicates that the address is not mapped to the memory, but is stored in the hard disk. Therefore, the required virtual storage address is immediately transferred to the memory; at the same time, when the system memory is insufficient, you can also swap out the existing virtual storage space to the hard disk to free up the physical memory space. In this way, to improve system performance and develop the virtual memory technology, a 32-bit cpu should also develop a new addressing technology to manage the virtual memory. This is throughPage Mechanism.
Due to the use of the page mechanism, the address obtained through the segment mechanism is only used as an intermediate address-linear address. This address does not represent the actual physical address, it represents the virtual space address of the entire process. There is also a process of converting a virtual address into a physical address.

Let's get to know the next page mechanism. It divides the memory into consecutive pages with a size of 4 kb per page. Different from the segment, the page is not an embodiment of the program functional block. A program function block may occupy multiple pages. Now the memory is like a book. The size of each page on one page is equal. Of course, we can quickly think of it. If we want to quickly find a page, we 'd better divide the book into chapters or sections, and then perform further queries. This is the role of the 32-bit cpu page Directory and page table. The page Directory is 4 kb in length. It can contain up to 1024 page Directory items. Each page Directory item is 32-bit and contains the address and related information of the page table. Therefore, the page Directory divides 4 GB space into 1024 page groups, each of which is 4 MB in size. The length of the page table is also 4 kb and 1024 page table items. Each page table item is 32-bit and contains the page address and other information. In this way, the 4 MB page group is divided into 1024 pages, each with a size of 4 kb. Therefore, finding a page is the process of first querying the page Directory and then querying the page table. To find the page Directory, we need to know its base address. In a 32-bit cpu, the 20-bit high in the CR 3 register is the address of the page Directory, because the 12-bit low in the page Directory is always 0, this ensures that the page Directory is always page aligned (4 kb per page ). Let's take a look at the linear address found through the 32-bit block mechanism. Its 10-bit height is the offset address of the page Directory. A total of 1024 page directories can be identified with 10 digits. With the addition of, you can find the page directory, and then find the base address of the page table through the page Directory. The 10 digits in the middle of the linear address are the offset of the page table, so you can find the page table. The base address of the last page table, coupled with the offset address of the page table characterized by the minimum 12 bits of, finds the page. The address of this page is the final physical address.

As mentioned above, the page mechanism is used for virtual memory technology. Therefore, the page Directory and page table have some attribute information besides the address information, such as whether the current page table is in memory. In this way, the system can conveniently manage the virtual memory to implement the swap function. This is not detailed here.

In general, 32-bit addressing first finds a 32-bit address through the 32-bit block mechanism. If paging is not used, it is a physical address. Otherwise, it is just a linear address, and then you can find the address of the page through the page Directory, page table, which is the final physical address. In fact, many details are not involved. For example, the Descriptor Table mentioned here is a Global Descriptor Table, and there is actually a Local Descriptor Table. For example, the descriptor only focuses on the address bit, the priority bit and other attribute bit are not described. However, a complete addressing image is present to us. It includes all the important mechanisms in the 32-bit CPU. For the remaining questions, you may wish to use the current method instead of asking questions.

 

Reason for 16-bit cpu segment management:

The 16-bit CPU has 20 inner address lines with the encoding range: 00000H ~ 0 FFFFFH, so it can directly access the physical space of 1 M (220) bytes. The 16-bit CPU Memory Unit offset registers (such as IP, SP, BP, SI, DI, and BX) are all 16 bits, and Their encoding range is only: 00000H ~ 0 FFFFH. In this way, if you use a 16-bit register to access the memory, you can only access the 64 K at the lowest end of the memory, and other memory will not be accessible. To effectively access 1 MB of storage space with 16-bit registers, the 16-bit CPU adopts the memory segment management mode and references the block register concept.

A 16-bit microcomputer divides the memory space into several logical segments. The requirements for each logical segment are as follows:		Figure 2.4 16-bit microcomputer memory segment Management
	The starting address (usually referred to as segment address) of the logical segment must be a multiple of 16, that is, the minimum 4-bit binary must be all 0;
	The maximum capacity of the logical segment is 64 KB, which is determined by the addressing space of the 16-bit register.
According to the above rules, 1 MB of memory can be divided into a maximum of 64 K segments, that is, 65536 segments (overlapping segments). At least 16 segments can be divided into non-overlapping segments. Figure 2.4 On the right shows the distribution of various logical segments in the memory, including connected segments (for example, C and D segments) and unconnected segments (for example, segments A and B) and overlapping segments (such as B and C ).

This memory segment management method not only enables two 16-bit registers to access 1 MB of memory space, besides, it has important practical value for program relocation, floating address encoding, and memory utilization improvement.

 

 

The role of the segment register:

Segment register is set for memory segment management. The 16-bit CPU has four segment registers, so its program can access four segments with different meanings at the same time. The reference relationship between the segment register and its offset is shown in 2.7.

The segment register CS points to the memory segment of the stored program, and the IP address is used to store the offset of the next instruction to be executed in this segment, you can combine them to get the next command to be executed in this memory segment.

The segment register SS points to the memory segment used for the stack, and the SP is used to point to the stack top of the stack and combine them together to access the top unit of the stack. In addition, when the offset uses the pointer register BP, the default segment register is also SS, and BP can be used to access the entire stack, not just to access the top of the stack.

The segment register DS points to the data segment, and the ES points to the additional segment. When the access operations are performed, the physical address of the storage unit can be obtained by combining one of the two and one offset. This offset can be one of the specific values, symbolic addresses, and pointer register values. The specific situation is determined by the instruction addressing method.

 

Generally, the default data segment register is DS, with only one exception. That is, when performing a string operation, the destination address segment register is set to ES. Of course, in general instructions, we can also change the segment register of the operands by using the prefix method.

 

Addressing Mode:

 

When the segment prefix is not used, the rule is: if the valid address contains BP, the default segment register is SS; otherwise, the default segment register is DS.

 

 

Addressing now:

Mov ah, 80 H

 

An operand is directly written in an instruction as a part of the instruction. This operand is called an immediate number. This addressing method is also called an immediate number addressing method.

Add ax, 1234 h mov ecx, 123456 H
MOV B1, 12 h mov W1, 3456 h add D1, 32123456 H

 

 

Register addressing

 

The operations required by the command are stored in a register, or the target operations are stored in the register. The addressing method that indicates the used register (that is, the memory aid of the Register) in the instruction is called the register addressing method.

1. The source operand is a register addressing method.

For example, add vard, eax add varw, ax mov varb, and BH.

VARD, VARW, and VARB are two-character, word, and byte memory variables. In Chapter 4th, you will learn how to define them.

2. The destination operand is the register addressing method.

For example, add bh, 78 h add ax, 1234 h mov ebx, and 12345678H.

3. Source and Destination operands are all register addressing methods.

For example, mov eax, ebx mov ax, bx mov dh, and BL.

 

Direct addressing

Mov bx, [1234 H],

 

 

 

 

 Register relative addressing mode

 

In memory, the valid address of an operand is the sum of the content of a base address register (BX, BP) or address change register (SI, DI) and the 8-bit/16-bit offset in the instruction. The formula for calculating the valid address is shown in the right formula. Mov bx, [SI + 100 H],

Base Address plus address change addressing

In memory, the valid address of an operand is the sum of the content of a base address register (BX, BP) and an address register (SI, DI. The formula for calculating the valid address is shown in the right formula.

Mov bx, [BX + SI],

 

The operations required by the command are stored in a register, or the target operations are stored in the register. The addressing method that indicates the used register (that is, the memory aid of the Register) in the instruction is called the register addressing method.

 

 

 

 Add address change addressing mode to relative base address

In memory, the valid address of an operand is the value of a base address register (BX, BP), a change register (SI, DI) and the 8-bit/16-bit offset in the command. The formula for calculating the valid address is shown in the right formula. Mov ax, [BX + SI + 200 H],

There are multiple equivalent writing modes for base address plus address change addressing. The following writing formats are correct and Their addressing meanings are consistent.

Mov ax, [BX + SI + 1000 H] mov ax, 1000 H [BX + SI]
Mov ax, 1000 H [BX] [SI] mov ax, 1000 H [SI] [BX]

However, the writing formats BX [1000 + SI] and si [1000 H + BX] are incorrect, that is, the registers used cannot be outside, this restriction also applies to the writing of the Register's relative addressing mode.

 

 

 

 

32-bit cpu addressing:

 

 

The formula for calculating the valid addresses with 32-bit address offset is shown in the right formula.

In 32-bit microcomputer systems, in addition to the preceding seven addressing modes, it also provides a more flexible and convenient memory addressing mode, the addressing range of the memory address is further expanded.

When a 16-bit register is used to access a storage unit, the base address register (BX and BP) and address register (SI and DI) can only be used as part of the address offset, however, when addressing with 32-bit registers, there is no such restriction. All 32-bit registers (EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP) it can be an integral part of the address offset.

When the 32-bit address offset is used for addressing, the memory address offset can be divided into three parts: a 32-bit base address register, a 32-bit address register that can be multiplied by 1, 2, 4, or 8, an 8-bit/32-bit offset constant, and the three parts can be combined as needed, saving one or two of them.

The 32-bit base address registers are EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP;
32-bit address change registers include EAX, EBX, ECX, EDX, ESI, EDI, and EBP (except ESP ).

The operands required by the instruction are stored in the memory, and the valid address of the operand is directly provided in the instruction. This addressing mode is direct addressing.

Usually, the operands are stored in the data segment. Therefore, the physical address is directly formed by the valid address provided by the data segment register DS and the instruction. However, if the segment is used beyond the prefix, operands can be stored in other segments

 

 

Indirect register addressing

 

 

In memory, the valid address of an operand is specified by one of four registers, namely SI, DI, BX, and BP.

Mov bx, [DI],