Cross-clock domain design "One"--slow to fast clock domains

Cross-clock domain design is a common problem in FPGA design, especially trigger signal synchronization design, often need to synchronize the slow clock domain trigger signal to the fast clock domain, the following is my work in the slow clock domain to the fast clock domain of the Verilog HDL design.

Trigger Cross Domain Design, Slow to fast clock Domain
Module Trig_ Crossdomain _s2f (
Input ClkB,
Input Rst_n,
Input Trigin_clka,

Output TRIGOUT_CLKB
);

reg [2:0] trig_dealy;

Always @ (Posedge ClkB or Negedge rst_n)
if (!rst_n)
Trig_dealy <= 0;
Else
Begin
Trig_dealy[0] <= Trigin_clka;
TRIG_DEALY[1] <= trig_dealy[0];
TRIG_DEALY[2] <= trig_dealy[1];
End

Assign TRIGOUT_CLKB = trig_dealy[1] & (! TRIG_DEALY[2]);

Endmodule

Cross-clock domain design "One"--slow to fast clock domains