Cstyle notes, R & amp; D must-read manual, 2nd Clock & amp; Power manager

Zookeeper has been tuned for a long time and found that the migration of uboot 2014.1 from 2410 to 2440 is always unavailable. It seems that the program is always running, and hang is in the place where the clock is set, therefore, it is necessary to carefully read the sections on clock and power management. Let's talk about the hardware configuration, 12 MHz crystal oscillator, we mentioned above the SDRAM (EM48AM1684VTE-6F) support maximum is 166 Mhz @ L3, cpu maximum support working frequency 400 MHz @ 1.3 V/300MHz@1.20V, however, the current power supply design of our board is designed because of the cost reduction by unscrupulous manufacturers. The two types of voltage are used to reach 1.25 V/3.3V. Therefore, refer to the following figure, it can be seen that the 1.3 MHz running on the board is okay, but it is estimated that the 1.25 MHz running is sufficient. The voltage of the MHz running for others' reference is V, while that of ours is V, which is barely supported, but the stability is hard to say. Let the machine be started first, and then there is time to verify it one by one. Two supported PLL, On-chip MPLL and UPLL, support slow clocks without PLL and connect/disconnect the clock to reduce power consumption:UPLL:UPLL generates the clock to operate USB Host/Device. USB block (48 Mhz ).
MPLL:MPLL generates the clock to operate MCU at maximum 400 Mhz @ 1.3V.Fclk Up to 400 MHz/Hclk Up to 136 MHz/Pclk Up to 68 MHz FCLK-> CPU core (ARM920T) HCLK-> AHB bus peripherals. as memory controller, the interrupt controller, the LCD controller, the DMA and USB host blockPCLK-> APB bus peripherals. as WDT, IIS, I2C, PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI.
So we are going to set the CPU to work at 400 Mhz and adopt FCLK: HCLK: PCLK =, Which is exactly 400 Mhz: 100 Mhz: 50 Mhz, which meets the maximum frequency requirement of the cpu PLL, so our task is to expand around this.

Power management:Four modes are supported: NORMAL mode, SLOW mode, IDLE mode, and SLEEP mode.
NORMAL mode: NORMAL working mode. All peripherals are enabled by default, with the highest power consumption. You can use CLKCON register to enable or disable the clock SLOW mode of a peripheral: Non-PLL mode, that is to say, shut down the PLL and use the external input clock. Here we use 12 MhzIDLE mode: Shut down the cpu clock, but keep the clock of other peripherals normal (you can also disable some peripherals ), the cpu can be awakened by the peripheral middle-end. SLEEP mode: the internal power is disabled to keep some of the wake-up power on. You can use the EINT [] or RTC alarm interrupt to wake up. You need to design two power supply PWREN pins to switch the power supply, however, I only use a route from MAX8860EUA18 to 1.25V for power supply from 3.3V to 1.25V on the board. It should not support the S3 function, but I may know it only after testing.
You can use an external crystal oscillator or an external input for MPLL and UPLL, and choose OM []. The crystal oscillator of 12 MHz is selected for our board, the MPLL system clock takes effect during reboot, but by default, the clock generated by its PLL is not used for various clock outputs of MPLL, MPLLCON register takes effect only once.
Phase-Locked Loop clock calculation and crystal oscillator frequency selection:MPLL Control RegisterMpll = (2 * m * Fin)/(p * 2 S) m = (MDIV + 8), p = (PDIV + 2), s = SDIVUPLL Control RegisterUpll = (m * Fin)/(p * 2 S) m = (MDIV + 8), p = (PDIV + 2), s = SDIV
PLL Value Selection Guide (MPLLCON) 1. FOUT = 2 * m * Fin/(p * 2 S), FVCO = 2 * m * Fin/p where: m = MDIV + 8, p = PDIV + 2, s = SDIV2. 600 MHz <FVCO <1.2ghz3.200 MHz <FCLKOUT <600MHz4. don't set the P or M value as zero, that is, setting the P = 000000, M = 00000000 can cause malfunction of the PLL. 5. the proper range of P and 1 <P <62, 1 <M <2486. when you set MPLL & UPLL values, you have to set the UPLL value first and then the MPLL value. (Needs intervals approximately 7 NOP ). (TRAP)
We can see from the following two figures that our requirements for Crystal Oscillator Selection, loop filter cap size and accuracy, and the timing sequence automatically set by the system clock during system reset, we also need to note that FCLK does not use MPLL output before the user sets the PLLCON register, but directly uses Fin, that is, 12 Mhz. Similarly, the PLL (UPLL) also needs to be set in advance, and the 48 MHz clock required by the USB will take effect.


An important comment from vendor. When we select our clock configuration, we need to pay attention to this Part with caution, here we will talk about whether the clock of the ARM core is FCLK or HCLK, which involves switching the cpu bus mode:
In addition to the clock switching mentioned above, we also need to pay attention to the ACPI status of various cpu operations, their previous switching methods, and the registers to be set before switching, what information is saved, for example, how to set the status of the data bus, how to enter the self-Refresh mode, GPIO status, usb status, wake-up source settings, and adc settings, supports ACPI hardware power supply design and so on. For the moment, let's take a look at it when it comes to power management. This part is here first.
In the last figure, I tried to debug the clock for a long time. It seems that the clock is partially set and OK, at least the system is working. This may not be a problem for the experts, but it is also a great challenge for cainiao. I am glad that the made it system is running, and the four LED lights used for debugging on the board are also properly lit.
Take a look at the semi-finished products. You can boot them to the uboot shell environment. The story here is a bit more complicated. You have also modified the amd_flash_info structure:
Reprinted please indicate the source Cstyle.z.zhou@gmail.com // http://blog.csdn.net/CStyle_0x007