Cycle issues for setup time and hold time

why calculate Setup time of the Slack need to consider adding cycles, Hold Time when you don't need it?

Summary one:

Because the data delay,launch edge and capture edge do not correspond to the same clock edge of the clock signal source clocks, due to the existence of the time of Setup, the addition cycle needs to be considered. When a single clock cycle is checked, the tool defaults to capture Edge-launch edge=1 cycles.

Hold time because the two correspond to the same clock along, so the cycle is not considered.

: The first clock rising edge of the REG1.CLK corresponds to the launch EDGE,REG2. A second clock rising edge of CLK corresponds to the capture edge. The two correspond to the first rising edge and the second rising edge of the clock source source clock CLK.

Summary two:

After the clock source CLK passes the network latency, the first rising edge reaches the REG1.CLK end and triggers the REG.1 data input reg.1.d data input. At this time, CLK first rising edge sent to REG2.CLK, it takes more time than the data latency is very short, so at this time to check the setup is not meaningful to the data transmission, increase the cycle, only meaningful.

When hold time, the first wave data stabilizes the input reg2.d and the second wave transmits to the reg2.d corresponding REG2.CLK the same clock signal, therefore does not need to add the cycle computation.

For multi-cycle:

For multiple clock cycles or multi-cycle path checks, if Setup is set to N, the hold needs to be set to N-1;
Thus, in most designs, a multicycle setup specified as N (cycles) should is accompanied by a multicycle hold constraint SP Ecified as N-1 (cycles).

There are two kinds of explanations, essentially the same.

Statement one: Hold of Capature Edge is prior to setup Capature Edge,this imposes a restriction this data can only change in the the one CY CLE before the Setup capture edge as the figure shows. Thus the data path must has a min delay of at least and clock cycles tomeet this requirement. Here's such a path report.
Argument two: Hold is a check on the same clock along the front and back of the two flip flop. Set the n-1 is to return to the n-1 cycle to do a hold check, meet the two flip flop on the same clock along. If there is no-hold default is to check n a valid clock edge, if the N>=2,hold check is not on the same clock effect along, the demand for hold is more than n-1 cycle, that is too harsh, the general timing can not converge.

Skew the size of Setup and the hold What is the impact?

According to the principle can be modified under the slack calculation method to:

Setup: slack= (Period+clock skew-setup time)-(REG1 cell delay+combinatinal logic delay)

Hold :slack= (REG1 cell delay+combinatinal logic delay)-(clock skew+hold time)

where Clock SKEW=TCLK2-TCLK1

So whether the calculation Slack,clock skew for setup or hold is more pessimistic, the more it tends to be 0. If the clock skew can be negative, the smaller the setup time the more pessimistic, the larger the hold time the more pessimistic.

" My understanding ."

When it comes to setup and hold-related calculations and concepts, the biggest difficulty is that, for different models and analysis angles, they correspond to the calculation method and the concept of understanding the algorithm and the argument is different, we are in the discussion, because the angle of the difference, it is easy to create an understanding deviation. In fact, the fundamental concept is only for the clock signal and data signal two parts, the essence of interoperability, and does not involve particularly difficult principle or formula.

Cycle issues for setup time and hold time