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CycloneIII design wizard-Article 1. chip selection
The company began to use the CycloneIII chip, so it intends to read the official documentation of Altera, AN466: Cyclone III Design Guidelines, and write a series of blog posts. According to the organization framework of the article, in addition to summarizing the content of the original document, I will also add a lot of my own experiences.
This note will not be completed once, and I will gradually complete it.
Article 1: chip selection
1. Consider device resources, including LE, ram resources, hardware multiplier, PLL, and global clock network.
In general, there must be margin for resources for FPGA design, otherwise the final time series convergence will be more difficult. I think it is appropriate to use around 80%. In addition to time series convergence, you may encounter unexpected problems in the design of resource usage over 95%.
A. LE is between 5K and 120 K. An estimate of the resources required by the design is 120 K. For most applications, it should be a big number.
B. The ram resource is 400K-3888Kbit. Note that the size of the ram block is 9 Kbit. Some modules, such as fifo, actually do not use 9 K resources. However, no matter how much you use, you have to use one ram (in some cases, 0.5 ram is used ). Therefore, consider whether the number of ram instances is sufficient.
C. The number of multiplier numbers is 23. Note that it is a 18*18 bit multiplier. In actual use, it depends on the multiplier precision required by the application.
D. The number of PLL is 2-4. Each PLL can output 5 clocks, and the general design is sufficient. If there is a lot of clock in the design, You have to carefully consider it.
E. There are 10-20 global clock networks. Generally enough. If there are a lot of clock or a lot of fan-out signals in the design, such as reset signals, you have to carefully consider it.
2. Pin, encapsulation, and migration considerations
A. Number of pins. Before the design, we need to consider how much ordinary I/O (LVTTL) is required. This should be better calculated. There are several levels, because one bank can only have one IO level. How many LVDS pins are needed, and few LVDS pins are needed for some small encapsulated devices.
B. encapsulation. Encapsulation affects the number of pins. It also affects the difficulty of welding. Of course, EQFP and PQFP are good for welding or disassembly. If it is BGA, we usually need to find a special welding Specialist (specialized tools are required), and the price is also expensive. Wiring difficulty: Use BGA and pay attention to ball pitch ). Of course, 0mm is better than 8mm. The F780 has more pins than the F484 outer ring. Of course, it also has better wiring. Volume: the size of the chip. For example, for mobile and handheld applications, you have to consider the size. However, the size is small and the wiring is difficult. Therefore, the layers of the pcb usually start from 6 layers and are not capped.
C. device migration. That is, different devices with different resources can be directly replaced with the same encapsulation. Of course, they all have to be CycloneIII devices. The advantage is that large-scale devices can be used in initial design. After the design is successful, the more economical devices can be replaced for mass production based on the actual resource usage. The specific model replacement is clearly stated in the document. If you consider the model replacement design, carefully check the pin document of each chip, and finally decide the pin definition of the chip when drawing the schematic. Here is a trick, that is, the pin definition of the largest chip, which is generally the closest, but there will also be modifications.
3. device Speed considerations
The speed is divided into-6,-7, and-8. -6 is the fastest and most expensive. The speed of each grade differs by 20%, including the internal operating frequency and IO speed. The actual maximum operating frequency of FPGA is independent of these numbers and is related to the specific design. In my experience, for a lot of code,-8 devices can run to around MHz. Previously, CycloneII-8 devices can only run to around MHz. It indicates that CycloneIII is more advanced than II.
Additionally, devices are divided into three types: commercial, industrial, and automotive. We generally purchase commercial devices. The difference lies in the temperature range and stability. If the operating temperature of the product is between 0 and 70 degrees, and the stability requirement is not too high, use the commercial level. High requirements, so pay more.
Download link to official documents: http://www.altera.com.cn/literature/an/an466.pdf
Subsequent parts:
Article 2. Early System Planning
Article 3 board-level design considerations
Article 4. Design and compilation
Article 5. Verification
Article 3. debugging
Article 1. Test
8th. Other considerations
CycloneIII design wizard-Article 2. Early System Planning
1. Early Power Consumption EstimationIt is necessary to estimate the power consumption of the chip early in order to design power supply and heat dissipation.
The following table lists the estimated power consumption of the Cyclone III device:
Http://www.altera.com.cn/support/devices/estimator/cy3-estimator/cycloneiii_epe_72sp1.xls
If the design has been basically completed, the quartusi software can also estimate the power consumption based on the actual design.
2. I/O support
A. Three types of I/O standards, including Single-ended (Single-ended), Voltage-referenced (reference Voltage), and Differential (Differential ). Each has its own advantages and disadvantages. However, in actual application, the standard used is usually determined by the FPGA-connected chip.
B. Flexible I/O bank. The I/O voltage of the eight banks and the Vref reference voltage can be different, but must be consistent within each bank. When the I/O voltage is determined, some compatibility is also available. For example, 2.5V and 3.3V compatibility.
C. External memory interface. Supports ddr, ddr2, and qdrII, and requires dedicated pins. Of course, the previously used sdram and sram are also supported, and no special pins are needed (it is better to handle the clock pin with caution ). The top and bottom banks are faster and support up to 200 MHz. Here is a brief introduction, for high-speed design, more query documents.
D. Pin-Out file. This file is generated after the quartuⅱ project is compiled. The description of the pin is the final function of the pin. Checking this file can help us clarify the problem. Take care of some of the multi-function pins.
3. Select the FPGA configuration Scheme
The following table shows the configuration scheme in the original article.
There are many configuration schemes, including
Active serial ():
Single-chip, with a 3rd-speed configuration by using the intel. The chip is expensive.
Active parallel (AP ):
Single-chip FLASH (INTEL P30, P33) with a configuration speed of 1st. Chip prices are cheap. However, it takes up to 40 FPGA pins (16 data + 24 addr ).
Passive serial (PS ):
Passive mode. Additional controllers are required. The configuration speed is 4th.
Fast passive parallel (FPP ):
In passive mode, additional controllers and flash chips are required. The configuration speed is 2nd. Flash chips are cheap. 8 FPGA pins (8 data) are required ).
Joint Test Action Group (JTAG) -- used for debugging
The selection of configuration scheme is controlled by MSEL pin.
Select whether fast power-on reset (POR) time is required for fast power-on.
Different packages support different configurations.
To select a configuration scheme, you need to consider the configuration time requirements.
In AS and AP modes, the DCLK of FPGA is output, and the maximum speed is 40 MHz. In PS and FPP modes, DCLK of FPGA is input, and the rising edge is sampled. The maximum speed is 100 MHz.
Download cables include:
USB-Blaster, which is currently the most common. The price is moderate, and the speed of downloading configuration files to FPGA is high. If you don't want to buy a pcb, you can download the pcb from the Internet and purchase the device.
ByteBlaster II, which is common and cheapest, but is slow to download. You can also do it yourself. When the device size is large, it will be very slow.
Ethernetblster, uncommon, expensive, and fast download speed.
Currently, USB-Blaster is strongly recommended unless it is too price sensitive.
You can use the JTAG interface of FPGA to burn the EPC configuration chip. The IP Core provided by Altera, Serial Flash Loader, must be used.
Using the max ii chip, PS or FPP mode, there is also the IP core of max ii Parallel Flash Loader, which is used to burn the FLASH through the max ii chip JTAG.
In AP mode, there is an IP Core FPGA-Based Parallel Flash Loader, and FLASH is written through the JTAG of FPGA.
4. configuration features
In AS and PS modes, you can select the compression mode to reduce the size of the configuration file.
Remote system upgrade, unfamiliar, to be supplemented
5. PLL
Powerful PLL functions, including clock frequency doubling, frequency division, phase shifting, programmable duty cycle, input clock switching, PLL cascade, PLL dynamic reconfiguration, dynamic phase shifting, Extended Spectrum clock, external clock output and control signals.
Compared with Cyclone II and Cyclone II, Cyclone III now supports dynamic reconfiguration of PLL.
The clock input of the PLL must use the dedicated clock input foot of the FPGA (dedicated clock
Input pins) or the clock output of another PLL. That is to say, the PLL can be cascaded.
Input clock switching: You can enter a dual clock for the PLL. When the input clock is invalid, it can be automatically or manually switched to another backup input clock.
The PLL has 5 outputs. If you want to output data to a dedicated external clock output pin, it is recommended that you use C0 to output data, so that the jitter is minimal. Other outputs can also be used.
If you have phase requirements for the input clock and the output clock of the PLL, you must understand the setting of the PLL phase compensation mode.
6. Chip internal debugging method
A. SignalProbe Incremental Routing does not change the current wiring and Leads internal signals to an unused I/O.
B. SignalTap II Embedded Logic Analyzer, which can capture real-time internal signals. Is the most common debugging tool. Requires a certain amount of LE and M9K resources. If you want to reduce the impact on the original design and the compilation time, you can reverse the original design and use the incremental compilation mode.
C. Logic Analyzer Interface is equivalent to a multi-path selector, which outputs multiple internal signals through a small number of pins. Which signals can be output without re-Compiling. Suitable for the logic analyzer that sends signals to the outside.
D. In-System Memory Content Editor modifies the Memory or constant value online.
E. In-System Sources and Probes can give a simple incentive signal to internal nodes and then capture the output.
F. Virtual JTAG Megafunction can give a simple incentive signal to internal nodes and capture the output. It is different from the above method.
A.3.3/3.0/2.5V ordinary I/O interface, if the external signal is the same voltage, do not consider too much. If the voltage is different, you have to carefully calculate whether there is any problem.
B. Pin settings considerations. The pins of single-ended and differential signals must be kept at a certain interval. If a single-ended signal of the reference voltage is used, there are also requirements for the interval. This is to reduce interference between signals. The quartusi software checks whether the pin distribution complies with the rules. If it does not, the design cannot be compiled.
If the actual signal is stable and does not flip (for example, keep high or low), you can set it through assignments to avoid rule checks. Setting Toggle Rate assignments for a single-ended pin removes the gap between this pin and the differential signal. The Output Enable Group assignment setting can meet the voltage reference signal interval requirements.
C. Reduce the simultaneous switch noise (SSN ). Method:
1). It is better to separate the simultaneously flipped pins and put them in two different banks.
2) high-speed pins. Stay away from VCC And GND and keep static and unused pins close to VCC And GND.
3) set slow slew rate and lower drive strength for the high-speed pin
4) make a good match (termination, or end-to-end)
For more information, see AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines.
D. Do not use pin settings. It is best to set it as input. If it is set to output and connected to an external circuit, the Chip Pin may be damaged.
E. Matching Scheme. Generally, the sending end of the signal uses serial matching, and the receiving end uses parallel matching. The matching resistance must conform to the transmission impedance. If possible, it is best to make a board-level simulation to select the matching resistance size. The Cyclone III chip has some pins that can be used to set the serial matching resistance (OCT) in the chip.
F. board-level simulation. Altera provides the IBIS and HSPICE models for Chip simulation.
2. Power Supply considerations
A. the power supply voltage includes
Vccint kernel voltage, 1.2 V
Vccio I/O voltage, each bank can be different. 3.3V is the most commonly used.
Simulation supply voltage of Vcca PLL, 2.5 V higher than that of Cyclone II Chip
Vccd_pll Digital Supply voltage, 1.2 V
Reference Voltage of Vref voltage reference signal
We recommend that you use linear regulator to power Vcca. For other digital voltages, use linear or switching regulators. The noise with linear regulator will be better.
The ferrite bead (ferrite bead) must be connected between the power supply chip and FPGA. The capacitor is connected to the power supply at one end and grounded at one end. The decoupling circuit is determined according to the specific design requirements. Tantalumcapacitors can be used if you have money ).
Pcb design, it is best to have a dedicated power supply layer.
B. Power Supply of PLL. The PLL contains simulator components and therefore has stricter power supply requirements.
1) The power supply to Vcca must be 20 mil in width
2) The Power Supply of Vccd should be clean.
3) All the power supplies of the pll must be connected, whether or not this pll is used.
4) use an independent linear regulator to power the PLL
5) Each Vcca and Vccd need to be coupled with a circuit. Altera has a reference design.
6) The Gnda should be connected to the isolated simulated ground.
3. device power-on
The Cyclone III chip supports hot switching and power-on Reset without additional reset chips.
The following describes the power-on process:
Cyclone III has no requirement on the power-on sequence of Vccint and Vccio voltage, as long as it increases monotonically. For the power-on time, if it is a normal POR, <50 ms. If it is set to fast POR, the power-on time is less than 3 ms.
To support hot swapping, consider more.
The POR circuit of the chip detects the voltage of the Vccint and Vcca. If it is lower than the threshold, the chip is reset. However, the Vccio voltage is not detected.
To sum up, the Cyclone III chip has good power management and saves a lot of external chips.
4. Configure Pin Connection
For specific configuration circuit, refer to the design. Note that it is different from Cyclone II. It is best not to use the old circuit (it seems that the old circuit can also run ipv_^ ).
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This is a common configuration method. The Reference Circuits for other configuration methods are also available. Note that any method must follow the reference circuit and cannot be connected by default.
5. configuration details
In the AS configuration mode, the Vccio of bank1 must be 3.3 V.
The DCLK of Cyclone III is 40 MHz, which is supported by EPCS16 and EPCS64 In the EPC device. However, the EPCS4 device has two process batches: 0.18 and 0.15. The former can only support 20 MHz, so it cannot be used with Cyclone III.
In AP mode, P30 and P33 flash are required. Similarly, flash needs to support 40 MHz DCLK. Note that TSOP encapsulation does not support this speed. FBGA encapsulation supports this speed.
Select the configuration Chip
Synchronous design: fully guarantees setup and hold time to reduce glitch and other interference. Use the input register of Cyclone iii I/O (note that it is not a common LE), so that the input signal of the chip can better filter out the glitch. You need to set "Fast Input Rgedister" to use this register.
We should adopt a good synchronization design, rather than using units such as LCELL to control the latency of specific paths. Because the latency of the FPGA internal path is uncertain, it will be changed in the design because of different layout and wiring, and will be changed due to temperature, voltage, and other factors in use, it will also change due to the difference in the process. To increase the stability of the design, try to increase the path margin during time series analysis. Although timing analysis is based on the timing characteristics of the chip in the worst case, it is good to leave a little margin while the design permits.
Clock: the clock is very important in the synchronization design.
A.
Of course, the clock must be input using a dedicated clock pin. Using a common I/O will cause a more serious clock offset. A high clock offset will cause a hold time violation. The global clock network is used inside the chip, and the global clock network can also be used for global Asynchronous Reset signals. The global clock network ensures the same latency from one point to multiple points. That is to say, the latency of a signal from the input pin through the Global clock network to various internal registers is the same although the path is different.
B.
Internal clock. Combination logic cannot process glitch. For input signals of the combination logic, use a high-frequency clock to filter glitch. For output signals of the combination logic, you can also use a high-frequency clock to filter glitch.
C.
Clock frequency division. You can use the PLL to divide the clock. The PLL can also precisely control the phase of the output clock.
D.
Clock flip. It is better to use PLL to change the clock phase than to use non-gate.
E.
Multiple clock input. For a pll, you can set a master clock and a backup clock.
F.
Clock gate. We recommend that you use the dedicated module altclkcrtl provided by Altera to implement the clock gate. If you only want to control the output steady state, you can add the ena signal to the input, so that the synchronization design is maintained. The clock is not synchronized with the non-clock. The control signal of the clock. The Glitch must be filtered out; otherwise, the output clock will be affected. The Clock source can be controlled as close as possible to reduce clock latency.
3. Chip-level reset
The Cyclone III chip supports chip-level reset, including clearing the content in the M9K. You need to enable the DEV_CLRn pin function. The default pin is normal I/O.
Iv. Register power-on Level
You can set whether the register is powered on to a high or low level. The default value is low. Set the Power-Up Level parameter.
5. design constraints
Quartus II provides the design constraints check function, through which the design reliability can be improved. Checks include clock, reset, asynchronous design, etc. This function is disabled by default.
6. hierarchical and team-based Design
Incremental compilation can reduce the time required for design iterations and the time required for time series convergence.
Partitioning design is the basis for incremental compilation. If a third-party integrated tool is used, several independent. vqm or. edf files need to be generated. At the top layer, it is best to connect each other between modules without any logic. The logic should be included in each module.
Time Series budget and resource allocation: the time series path in the module can be optimized separately. However, for cross-partition time series paths, they can only be optimized after integration. These time series paths can meet the requirements by adding constraints. Resource allocation should also be calculated in advance to avoid conflicts after integration. In addition to common resources, note that global clock resources are also limited.
Bottom-up and team-based processes: Before designing the underlying layer, you must know the information about the top layer, including Pin allocation, physical constraints, and timing requirements. Quartus II provides some scripts (Generate bottom-up design partition scripts) to transmit top-level information to the bottom-layer.
You can use LogicLock to physically partition the design. LogicLock is usually performed only for modules that have difficulty in timing. LogicLock for general modules reduces the layout flexibility. The Chip Planner function of Quartus II can precisely deploy registers, estimate physical latencies, and observe the connections between modules.
The following is the content of the next article:
VII. Power Consumption Optimization
VIII. I/O considerations
9. PLL considerations
10. Configure software settings
11.
Effective pin layout CycloneIII design wizard-Article 4. Design and compilation (II)
Quartus II software supports integrated and layout cabling options for Power Consumption Optimization. However, timing constraints have a higher priority than Power Consumption Optimization. The former must be satisfied before the latter can be considered. The software contains a wizard for Power Consumption Optimization, which is easy to use. DSE is also a good optimization tool.
The following are some methods to optimize power consumption from the design perspective:
1.
Clock Power Consumption management. Quartus II automatically optimizes the power consumption of the clock network. You can also use the clock to reduce power consumption.
2.
Memory power consumption. To reduce memory power consumption, use the memory clock signal.
3.
I/O power consumption. Factors that determine I/O power consumption include load capacitance, output frequency, and output voltage swing. The voltage swing of the I/O standard for voltage reference (such as SSTL) is lower than that of LVTTL and LVCMOS, so the dynamic power consumption is lower. However, static power consumption is higher.
4.
Register insertion. Inserting registers in complex logic can reduce the dynamic power consumption caused by glitches, but also increase the Register power consumption.
5.
Structure optimization. Use the DSP module for mathematical computing, rather than using LE. Large Shift Registers use ram resources to implement FIFO instead of using LE. This can reduce power consumption.
VIII. I/O considerations
The I/O features of the Cyclone III chip are more powerful than before. The I/O design process includes creating pin-related configurations to verify that the configurations comply with the rules.
Pin Planner ):
Package View (default View): provides a visual chip encapsulation that allows you to allocate pins more intuitively to avoid congestion. The chip encapsulation can be displayed in different ways, including sub-bank, differential pin, and allocated pin. If you cannot tell which side of the chip is TOP, you can use Show Edges. Then you will know that bank12 is LEFT, bank34 is BOTTOM, bank56 is RIGHT, and bank78 is TOP.
Pad View: Provides the pin distribution sequence of the chip core (bare chip. Note that some pin distribution rules may be hard to understand after Chip encapsulation (such as BGA encapsulation), but you can see the distribution of bare pins.
Pin Migration View: if you want to consider device Migration (compatible) during design, it is most convenient to use this View. Select a compatible device, the final selection of each pin is generated directly. Encapsulate the view results.
Assignment Editor, pin-related Configuration:
1.
Current Strength: the output Current size can be configured for each I/O standard. Note that increasing the current will improve the I/O performance, but will also increase the noise. The current is too small, especially for the output clock signal. Therefore, it is important to select an appropriate current.
2.
Slew rate control: for high-speed data bus, we recommend that you enable this setting to reduce SSO interference. This setting only supports single-end I/O standards, with a current greater than or equal to 8mA. The specific use of this setting will be supplemented.
3.
In-chip serial match (OCT): OCT has two modes: Calibration and non-calibration. In non-calibrated cases, the resistance is 25 euro and 50 euro by default. In the CALIBRATION mode, the RUP and RDN pins need to be connected to 25 euro or 50 euro precision resistors. The chip will be calibrated during FPGA configuration to set more accurate OCT values.
4.
Dedicated differential output buffer unit: the I/O bank of left and right has this unit. The maximum output speed of LVDS is 840 Mbps and no external sending matching resistance is required. This unit can also pre-increase the output signal. When a signal is transmitted over a cable, the attenuation of the high-frequency component is greater than that of the low-frequency component. Therefore, the high-frequency components can be amplified to reduce the imbalance between the high-frequency components and the low-frequency components at the receiving end. Note that the configuration option is named (Programmable Pre-emphasis ).
9. PLL considerations
Cyclone III has four independent PLL units (EP3C5 and EP3C10 have only two ). The input clock of the PLL can only be a dedicated clock input or an output clock of the other PLL. The C0 of the PLL is output to the dedicated clock output pin to achieve the best wiring effect.
The PLL module can perform functional simulation and timing simulation.
10. Configure software settings
1.
Optional configuration pins. Enable user-supplied start-up clock (CLKUSR). This option is used to control whether to use an external clock to initialize FPGA. FPGA uses a 10 MHz internal clock by default for initialization. Enable INIT_DONE output. If this option is enabled, the pin increases from low to high when FPGA configuration is complete. If used, the external pull of 10 k euro is required.
2.
Automatic Reconfiguration. Enable the auto-restart configuration after error option. When an FPGA configuration error occurs, it is automatically reconfigured.
3.
Estimate the configuration file size. The size of the file in the rbf format is closest to the size of the original uncompressed file.
4.
Convert the configuration file format. The original sof files can be converted to pof, hexout, rbf, ttf, rpd, and jic formats. Pof and jic are supported by the Quartus II burning software. Other formats are used for other burning software. To configure multiple devices, you can combine multiple sofs and convert them into a configuration file. Note that the order of combination is related to the configuration order.
XI,
Effective pin Layout
1.
I/O configuration check. Start I/O Assignment AnalysisCommand, which can be used to checkI/OWhether the configuration is in violation.
2.
DC-related. The input or output current is too large to damage the chip. A typical example is that the output high pin is directly grounded, and the output low pin is directly connected to Vcc. Each I/O pin has a maximum output of 40mA and an input of 25mA. If the PIN is to be pulled up or down, it must be connected to the external resistance. Note that the total output current of the continuous pin is limited. Therefore, it is necessary to distribute pins as much as possible and limit the current properly.
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