D-type trigger

Document directory

• D Trigger
• A binary counter consisting of a J-K trigger
• 8-bit metashift register

D
Trigger

By J-K
Binary counters composed of triggers

8
Bitwise shift register

D Trigger

Latches
It is a basic memory device that can store a piece of metadata. Because it is a time series circuit, it does not need clock input, it will change the output according to the input.

Unlike latches, a trigger is a memory device for clock control. A trigger has a control input signal.
(Clock ). The clock signal enables the trigger to change the output status only according to the input signal at a specific time point. If the trigger is only in the Clock from L to H (h to L)
The time when the conversion is received, it is said that this trigger is triggered by the rising edge (descending edge.

A trigger can be used to store one bit of data. By connecting several triggers together, you can store multi-bit meta data, which can be used to indicate the status of the sequencer, the counter value, and the computer
The ASCII code in the memory or other materials.

D triggers are one of the most common triggers. For the D Trigger triggered by the rising edge, the output Q will follow the state of input d only when the clock is switched from L to H.
Change. In other cases, Q remains unchanged. Figure 1 shows the sequence of the D Trigger triggered by the rising edge. Table 1 shows its truth table.

Figure 1: sequence diagram of the D Trigger triggered by the rising edge

Table 1: D Trigger truth table

Set and reset are two additional inputs in the D trigger that can block clock operations. D. When the trigger works normally, set and reset must both be set to 1.

The earliest electronic trigger was invented in 1919. In the time series control system, the four most commonly used triggers are: T-type trigger, S-R trigger, J-K trigger
And D triggers.

A binary counter consisting of a J-K trigger

A counter is a device that can store or display the number of occurrences of a specific event, usually related to clock signals. In electronics, counters can be made using simple memory devices, such as triggers.

J-K triggers are one of the most commonly used triggers. Table 2 is the truth table that drops along a trigger to the J-K.

Table 2: J-K trigger truth table

In Figure 2, the four descent edges trigger the J-K trigger to connect together in concatenate mode to form a binary counter. The output Q of each trigger is connected to the next trigger.
Set the input J and K of each trigger to 1 according to the truth table. Therefore, the trigger changes its status every time it is switched from H to L.

Figure 2: Timing Diagram of a counter composed of a J-K trigger

In this binary counter, four outputs A to D represent a 4-bit binary number, where A is the lowest valid bits (LSB) and D is the highest valid bits
(MSB ).

The four-bit binary number increases by 1 with the arrival of each Clock cycle. The counter ranges from (0) 10 to (15) 10, and then returns
(0) 10 and keep repeating. See table 3.

 

Decimal	Binary
	D	C	B	A
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
10	1	0	1	0
11	1	0	1	1
12	1	1	0	0
13	1	1	0	1
14	1	1	1	0
15	1	1	1	1

Table 3: truth table of a 4-bit binary counter

8-bit metashift register

In digital
In a circuit, registers are used to store data. Generally, two or more registers have a common clock (clock)
The input trigger. In computers, registers are often used to store a series of bitwise elements (or bittuples.

A shift register is a multi-bit register. During each clock conversion time, the data in the register is shifted by a bit. A group of triggers in the shift register
The output of each trigger is connected to the input of the next trigger. Therefore, data is moved one by one to the next trigger when the clock input is triggered.

For an 8-bit metashift register, when each clock is converted from L to H, the shift register reads the input data and sends it to the output A0. A0
A6 the original values of each bit will be moved to the next bit.
(That is, a0 is moved to A1, A1 to A2 ,......, A6 to A7), and the A7 value will be removed from the register. Table 1 describes the operation of the Register.

 

	A0	A1	A2	A3	A4	A5	A6	A7
Initial status	0	0	0	0	0	0	0	0
Clock cycle 1	1	0	0	0	0	0	0	0
Clock cycle 2	0	1	0	0	0	0	0	0
Clock cycle 3	0	0	1	0	0	0	0	0
Clock cycle 4	0	0	0	1	0	0	0	0
Clock Cycle 5	0	0	0	0	1	0	0	0
Clock cycle 6	0	0	0	0	0	1	0	0
Clock period 7	0	0	0	0	0	0	1	0
Clock cycle 8	0	0	0	0	0	0	0	1

Table 4: Shift Register procedures in eight clock cycles

The input and output of the shift register can be in serial or parallel mode. Serial input means that the device reads data one by one, while parallel output means that
Output. For example, a shift register with serial input and parallel output reads data one by one, and all output elements are output at the same time.

Most circuits work in parallel mode with multiple single-bit elements, while the serial interface has the advantages of simple structure. Therefore, a device-shift register is required to complete the serial interface and parallel
Conversion between interfaces.

The shift register can be used as a simple delay circuit. Data signals at different output ends (A0 to A7) with different clock cycle latencies can be obtained.

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