Data read/write method and source code of NAND Flash

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Data read/write method and source code of NAND Flash

The data in NAND Flash is bit
In memory cell. Generally, only one bit can be stored in a cell. These cells are connected to bits in 8 or 16 units.
Line to form the so-called byte (X8)/Word (x16), which is the location width of the NAND device. These lines form a page
Flash has multiple structures. The NAND Flash I use is k9f1208. The following content is for Samsung's k9f1208u0m). Each page contains 528 bytes, each 32 bytes.
Pages form a block, sizeof (Block) = 16 kbyte. 1
Block = 16 Kbyte, 512 Mbit = 64 Mbyte, numberof (Block) = 4096 1 block = 32 page,
1 page = 528 byte = 512 byte (main area) + 16 byte (spare Area)
NAND Flash reads and writes data on pages, and erased data on blocks. In this way, three types of addresses can be formed: -- block address -- page address -- column address.

For NAND Flash, the address and command can only be transmitted on I/O [], and the data width is 8 bits.
9bit is required for 512byte. For the 528byte series nand, The 512byte is divided into 1st half and 2nd.
Half, each access is selected by the address pointer command. A [] is the so-called column address. 32 pages require 5bit
Occupies a [], that is, the relative address of the page in the block. The block address is expressed by BITs above A14, for example, 512 MB.
A total of 4096 blocks. Therefore, 12 bits are required, that is, a []. If it is a 528 byte/Page NAND of 1 Gbit
Flash, the block address is represented by a [26:24. While page address is blcok address | PAGE
Address in block nand flash: block address | PAGE address in
Block | halfpage pointer | the transfer order of column address is column address, page
Address, block address. Because the address can only be transmitted on I/O [], it must be shifted. For example, for the 512 Mbit
X8 NAND Flash, address range: 0 ~ 0x3ff_ffff, as long as it is a numerical value in this range, the address is valid. Take nand_addr as an example: 1st
The step is to pass the column address, that is, nand_addr [], which can be passed to I/O [] without shift, while halfpage
Pointer: bit8 is determined by the Operation Command, that is, the command determines on which halfpage to read and write. The true bit8 value is don't care.
Step 2: Shift nand_addr to 9 places right, and upload nand_addr [] to I/O [] 2nd
Step 2: Place nand_addr [24:17] On I/O Step 3: Place nand_addr [25] On I/O. Therefore, the entire address transfer process requires 4
Step 4: Step addressing. If the capacity of NAND Flash is less than 256 Mbit, block adress
The maximum bit is bit24, so addressing takes only three steps. Next, we will give a brief description of the x16 NAND flash device. Because the main of a page
The size of an area is 256 words, which is still equivalent to 512 bytes. However, there is no such thing as 1st halfpage or 2nd halfpage.
So bit8 becomes meaningless, that is, bit8 is totally unnecessary at this time, and the address transmission is still the same as that of X8 devices. In addition, x16
And X8 are used in the same way.
Just as the disk of a hard disk is divided into tracks, each track is divided into several sectors, one NAND Flash is also divided into several blocks, and each block is divided into dry pages. Generally, the relationship between blocks and pages varies with chips. The typical allocation is as follows:
1 block = 32 page
1 page = 512 bytes (datafield) + 16 bytes (OOB)

 

It should be noted that all flash reads and writes start with a page, but flash must be erased before reading and writing, while Flash is written in a block. Required
Note that 256 bytes is theoretically divided into 1st half and 2SD half, each of which occupies bytes.
The k9f1208u0b we discussed has a total of 4096 blocks, so we can know that the flash capacity is 4096 * (32*528) =
69206016 bytes = 66 MB
But in fact, the last 16bytes on each page is used for storing the verification code and other information, and cannot store actual data. Therefore, we can actually operate on a chip with a capacity of 4096
* (32*512) = 67108864 bytes = 64 MB by, 1 page by 528 in total
Bytes, these 528 bytes are arranged in order from top to bottom in column units (1 column represents a byte. 0th million behaviors 0th bytes, 1st million behaviors 1st
Byte, and so on, each row is composed of eight digits, each representing 1 bit in 1 byte ). These 528bytes are divided into two parts by function: Data
Field and spare field, where spare
The field occupies 16 bytes of 528bytes, which is used to store the verification code During read/write operations. Generally, no common data storage zone is required.
16 bytes. The remaining bytes are the data we use to store data.
Field, so although there are 528 bytes on a page, we only calculate the capacity by bytes.

There are two read commands:
In read1 and read2, read1 is used to read data in the data field, while read2 is used to read data in the spare field. For Nand
For flash, the smallest unit of read operations is page. That is to say, when the starting position of the read operation is given, the read operation will start from this position and continue to read the last page.
Byte (which can include spare field ).

Addressing of NAND Flash

The address register of NAND Flash Splits a complete NAND flash Address into column address and page address.

 
Column address: column address
. Column address specifies a byte on the page. Specifying this Byte actually specifies the read/write start address of the page.

Paage address: page address
. Because the page address is always aligned with bytes, its 9-bit low is always 0. Determine the page on which the read/write operation is performed.

Read1 command
When we get a NAND flash Address src_addr, we can break down the column address and page address as follows:

Column_addr = src_addr % 512; // column address
Page_address = (src_addr> 9); // page address

You can also think that the a0 ~ Of a NAND flash Address ~ A7 is its column_addr, A9 ~ A25 is its page address. (Note that the address bits A8 does not appear, that is, A8 is ignored. Here you will learn why)

Read1
Command operations are divided into four cycle. After sending the READ command 00h or 01 H (for the difference between 00h and 01h, see the description below), four cycle sending parameters will be divided. 1st. cycle is
Send column address. 2nd. cycle, 3rd. cycle, and 4th. cycle specify the page
Address (each time the data sent to the address register can only be 8 bits, so the 17-bit page address must be sent three times.

The read1 command contains two Command Options: 00h and 01 H. Here we see two read-only messages. What do you realize? Yes, 00h is used for reading and writing 1st St
Half command, while 01h is used to read 2nd
Half command. Now I can explain to you why k9f1208u0b's datafield is divided into two half.

 
As mentioned above, 1st st. cycle of read1 sends the column address, assuming that the column
If the address is 0, the read operation reads the last byte (including spare) of this page from byte 0th.
Field), if the column address I specified is 127, the situation is the same as the previous one, but you do not know it, it is used to pass the column
There are eight address data lines (I/O0 ~ I/O7, corresponding to a0 ~ A7, Which is why A8 does not appear in the address bit we pass), that is, what we can specify
Column
Address range: 0 ~ 255, but do not forget that the datafield of a page is composed of 512 bytes. Now I want to specify that the READ command starts from 256th bytes.
Start reading this page. What will happen? I must set column address to 256, but Column
Address can only be 255 at most, which causes data overflow... For this reason, we divide the data field into two half-partitions.

Address) in 0 ~ In 255, we use the 256 H command. When the starting address for reading is ~ 511, The 01h command is used. Suppose now I want to specify to open
Read this page, then I will send the command string as follows:

Column_addr = 256;
Nf_cmd = 0x01; read from 2nd half
Nf_addr = column_addr & 0xff; 1st Cycle
Nf_addr = page_address & 0xff; 2nd. Cycle
Nf_addr = (page_address> 8) & 0xff; 3rd. Cycle
Nf_addr = (page_address> 16) & 0xff; 4th. Cycle

Here, nf_cmd and nf_addr are the nandflash command registers and address register address unreferencing. I usually define them as follows:

# Define rnfcmd (* (volatile unsigned char *) 0x4e000004) // nadd flash command
# Define rnfaddr (* (volatile unsigned char *) 0x4e000008) // NAND flash Address

In fact, when nf_cmd = 0x01, the 8th-bit (A8) in the address register will be set to 1. (for example, the A8 bit is not in the address we passed, this bit is actually based on the hardware circuit

The commands 01h or 00h are used to set the high or low position). In this way, we pass the value of column_addr to 256, which is automatically changed to 1 due to data overflow, but the A8 bit is already due to nf_cmd.
The relationship = 0x01 is set to 1, so the value passed to the address register is changed:

A0 A1 A2 A3 A4 A5 A6 A7 A8
1 0 0 0 0 0 0 1

The eight digits represent exactly 256, so that the read operation will start to read data from byte 256th (byte 0th of 2nd half) on this page. Nand_flash.c contains three functions:

Void nf_reset (void );
Void nf_init (void );
Void nf_read (unsigned int src_addr, unsigned char * desc_addr, int size );

Nf_reset () will be called by nf_init. Nf_init () is the nand_flash initialization function. Before performing any operation on NAND Flash, nf_init () must be called.

 
Nf_read (unsigned int src_addr, unsigned char * desc_addr, int size); For read functions, src_addr is the address on NAND Flash, desc_addr is the memory address, and size is the length of the read file.

 
There are two macros in the nf_reset and nf_read functions:

Nf_nfce_l ();
Nf_nfce_h ();

You can see that nf_nfce_l () must be called before each operation on NAND Flash, and nf_nfce_h () must be called at the end of the operation. These two macros are used to start and disable flash chips (chip selection/cancel chip selection ). For nf_reset:

 
Rnfconf = (1 <15) | (1 <14) | (1 <13) | (1 <12) | (1 <11) | (tacls <8) | (twrph0 <4) | (twrph1 <0 );

This line of code initializes the nandflash control register, and rnfconf is the configuration register of NAND Flash. For specific functions of each bit, see the S3C2410 Data Manual.
For example, if I want to read 5,000th bytes from 1024 bytes in NAND Flash to 0x30000000 in memory, we call the READ function as follows:

Nf_read (5000, 0 x );

Let's analyze the 5000 src_addr .:

According

Column_addr = src_addr % 512;
Page_address = (src_addr> 9 );

We can conclude that:

Column_addr = 5000% 512 = 392
Page_address = (5000> 9) = 9

So we can know that the address 5000 is at the 9th byte on page 392nd, so our nf_read function will send the command and parameters as follows:

Column_addr = 5000% 512;
> Page_address = (5000> 9 );

Nf_cmd = 0x01; read from 2nd half
Nf_addr = column_addr & 0xff; 1st Cycle
Nf_addr = page_address & 0xff; 2nd. Cycle
Nf_addr = (page_address> 8) & 0xff; 3rd. Cycle
Nf_addr = (page_address> 16) & 0xff; 4th. Cycle

After sending the above commands and parameters to the nandflash command register and address register, we can read data from the rnfdata register (nandflash data register ..

 
I use the following code to read data .:

For (I = column_addr; I <512; I ++)
{
* Buf ++ = nf_rddata ();
}

Each time a page is read, the Data Pointer falls into column 0 (byte 0) of the next page ).
The source code is as follows:
/*
Www.another-prj.com

Author: caiyuqing

This code is only for communication and learning and cannot be used for commercial development.
*/
# Include "S3C2410. H"
# Include "nand_flash.h"
Static unsigned char sebuf [16] = {0xff };
// Configure //--------------------------------------------------------------------------------------
Unsigned short nf_checkid (void)
{
Int I;
Unsigned short ID;
Nf_nfce_l (); // chip enable

Nf_cmd (0x90); // read ID
Nf_addr (0x0 );
For (I = 0; I <10; I ++); // wait twb (100ns)

Id = nf_rddata () <8; // maker code (k9s1208v: 0xec)
Id | = nf_rddata (); // devide code (k9s1208v: 0x76)

Nf_nfce_h (); // chip enable
Return ID;
}
// Configure //--------------------------------------------------------------------------------------
Static void nf_reset (void)
{
Int I;
Nf_nfce_l (); // chip enable
Nf_cmd (0xff); // reset command
For (I = 0; I <10; I ++); // twb = 100ns.
Nf_waitrb (); // wait 200 ~ 500us;
Nf_nfce_h (); // chip disable
}
// Configure //--------------------------------------------------------------------------------------
Void nf_init (void)
{
Rnfconf = (1 <15) | (1 <14) | (1 <13) | (1 <12) | (1 <11) | (tacls <8) | (twrph0 <4) | (twrph1 <0 );

// 1 1 1 1 1 xxx r xxx, r xxx
// En r eccr nfce = H tacls twrph0 twrph1
Nf_reset ();
}
// Configure //--------------------------------------------------------------------------------------

Void nf_read (unsigned int src_addr, unsigned char * desc_addr, int size)
{
Int I;
Unsigned int column_addr = src_addr % 512; // column address
Unsigned int page_address = (src_addr> 9); // page addrress
Unsigned char * Buf = desc_addr;
While (unsigned INT) BUF <(unsigned INT) (desc_addr) + size)
{
Nf_nfce_l (); // enable Chip

/* Nf_addr and nf_cmd are nand_flash addresses and command registers for unreferencing */
If (column_addr> 255) // 2end halft
Nf_cmd (0x01); // read2 command. CMD 0x01: read command (start from 2end half page)
Else
Nf_cmd (0x00); // 1st halft?

Nf_addr (column_addr & 0xff); // column address
Nf_addr (page_address & 0xff); // page address
Nf_addr (page_address> 8) & 0xff );//...
Nf_addr (page_address> 16) & 0xff );//..
For (I = 0; I <10; I ++); // wait twb (100ns )/////??????
Nf_waitrb (); // wait tr (max 12us)

// Read from main area
For (I = column_addr; I <512; I ++)
{
* Buf ++ = nf_rddata ();
}
Nf_nfce_h (); // disable Chip
Column_addr = 0;
Page_address ++;
}
Return;
}