Debug lattice debugging of the sgmii.

Recently debugged the lattice Sgmii interface. The initial schema for the project is probably the same, for debugging.

The architecture on this side of the FPGA is tri_mac to sgmii and then out of PCs. In fact, Sgmii nuclear comes with a PCs core, the most deceptive is that PCs must be external clocks, and finally there is no way to generate only a PCs core and Sgmii check-up. As a result of Mdio, we did not use it here. The force output is used. I debug for two days only to find that may be the switch side Setup may have a problem, the use of the BCM56634, the beginning is not familiar with, and finally to ask someone else only to turn it off the automatic connection. And then it's OK. I put the switch chip on this side of the configuration as follows:

Finally attached to my serdes this side of the code;

' Timescale 1ns/100psmodule TOP_HB (//G/mii Interfacedata_in_mii,en_in_mii,err_in_mii,data_out_mii,dv_out_mii,err_ out_mii,col_out_mii,crs_out_mii,//GB Timing Referencesin_clk_125,in_ce_sink,in_ce_source,out_clk_125,out_ce_sink , out_ce_source,//SERIAL GMII Interface refclkp,refclkn,hdinp0, Hdinn0, Hdoutp0, hdoutn0,//Control Interfacegbe_mode, sgmii_mode,rst_n,//Host Bushclk,hcs_n,hwrite_n,haddr,hdatain,hdataout,hready_n,//debug Portdebug_link_timer_      Short,mr_an_complete);//I/O declarationsinputrst_n;//System Reset, Active lowinputhclk;input gbe_mode;    GBE Mode (0=sgmii 1=gbe) input sgmii_mode;    SGMII PCS Mode (0=mac 1=phy) inputin_clk_125; GMII input Data Path clock 125mhzinputin_ce_sink; outputin_ce_source; input [7:0]data_in_mii;//g/mii Incoming Datainpu    ten_in_mii;//g/mii Incoming Data validinputerr_in_mii;//g/mii Incoming errorinputout_clk_125; GMII output Data Path clock 125mhzinputout_ce_sink; outputout_ce_source; output [7:0]data_out_mii;//g/mii outgoing dataoutputdv_out_mii; G/mii outgoing Data validoutputerr_out_mii;//g/mii outgoing erroroutputcol_out_mii;//G/MII Collision Detect OUTPUTCR s_out_mii;//g/mii Carrier Sense Detect inputrefclkp;inputrefclkn;//exemplar attribute refclkp nopad true//Exemplar attr Ibute refclkn nopad trueinputhdinp0;//Incoming SGMII (on SERDES) inputhdinn0;//Incoming SGMII (on SERDES)//Exemplar attr Ibute hdinp0 nopad true//exemplar attribute hdinn0 nopad trueoutputhdoutp0;//outgoing SGMII (on SERDES) outputhdoutn0;//           Outgoing SGMII (on SERDES)//exemplar attribute hdoutp0 nopad true//exemplar attribute hdoutn0 Nopad trueinput Hcs_n;input hwrite_n;input [5:0] haddr;input [7:0] hdatain;output [7:0] Hdataout;output Hrea  Dy_n;input debug_link_timer_short;output mr_an_complete;//Primary g/mii Outputs--latched before leaving Fpgareg [7:0]data_out_mii;regdv_out_mii;regerr_out_mii;regcol_out_mii;regcrs_out_mii;// G/mii signals from input latches to SGMII Channelreg [7:0]data_buf2chan;regen_buf2chan;regerr_buf2chan;//G/MII Signals F Rom SGMII channel to output latcheswire [7:0]data_chan2buf;wire dv_chan2buf;wire err_chan2buf;wire Col_chan2buf;wire CRS _chan2buf;//8-bit Interface signals from SGMII channel to Quadpcs/serdeswire [7:0]data_chan2quad;wire kcntl_chan2quad;w IRE Disparity_cntl_chan2quad;wire xmit_autoneg;//8-bit Interface signals from Quadpcs/serdes to SGMII Channelwire [7:0]d Ata_quad2chan;wirekcntl_quad2chan;wiredisp_err_quad2chan;wirecv_err_quad2chan;wirelink_status;wireserdes_ recovered_clk;wirerefclk2fpga;//Misc signalswire mdin;wire mdout;wire mdout_en;wire mr_an_enable;wire mr_restart_an; Wire [15:0] Mr_adv_ability;wire mr_an_complete;wire mr_page_rx;wire [15:0] Mr_lp_adv_ability;wire Mr_main_reset;wire Mr_loopback_enable;wire [1:0] mr_speed_selection;wire mr_power_down;wire mr_isolate;wire mr_duplex_mode;wire Mr_col_ Test;wire Mr_unidir_enable;wire An_link_ok;wire debug_link_tImer_short;wire [1:0] operational_rate;wire tx_pll_lol;wire rx_cdr_lol;wire quad_rst;wire tx_pcs_rst;wire Rx_pcs_rst; Wire Rx_serdes_rst;wire Nc_1;wire nc_2;wire nc_3;//Active high resetwire rst;///assign rst = ~rst_n;//Instantiate Globa L Reset CONTROLLER//GSR Gsr_inst (. GSR (Rst_n));//pur Pur_inst (. PUR (1 ' B1)); Tx_reset_sm tx_reset_sm (. Rst_n (Rst_n),. Refclkdiv2 (in_clk_125),. tx_pll_lol_qd_s (Tx_pll_lol),. Rst_qd_c (Quad_rst),. Tx_pcs_rst_ch_c ({nc_3, nc_2, Nc_1, Tx_pcs_rst});//Buffer Incoming MII Data at Primary i/oalways @ (Posedge I n_clk_125 or Negedge rst_n) beginif (rst_n = 1 ' b0) Begindata_buf2chan <= 8 ' d0;en_buf2chan <= 0;err_buf2chan <= 0; Endelse Begindata_buf2chan <= Data_in_mii;en_buf2chan <= en_in_mii;err_buf2chan <= err_in_mii;endend//Buffer Outgoing MII Data at Primary i/oalways @ (Posedge out_clk_125 or Negedge rst_n) beginif (rst_n = = 1 ' b0) begindata_out_mii &L t;= 8 ' d0;dv_out_mii <= 0;err_out_mii <= 0;col_out_mii <= 0;crs_out_mii <= 0;endelSe begindata_out_mii <= data_chan2buf;dv_out_mii <= dv_chan2buf;err_out_mii <= err_chan2buf;col_out_mii <= Col_chan2buf;crs_out_mii <= crs_chan2buf;endend/*//Control interfaceinput rst_n; input Signal_detect input gbe_mode; input sgmii_mode; input [1:0] operational_rate; input debug_link_timer_short; I Nput force_isolate; input force_loopback; input force_unidir; *///Instantiate SGMII IP coresgmii u1_dut (//Clock and Reset.rst_n (Rst_n),. tx_clk_125 (in_clk_125),. tx_clock_enable_s Ink (In_ce_sink),. Tx_clock_enable_source (In_ce_source),. rx_clk_125 (),. Rx_clock_enable_sink (),. Rx_clock_enable_ Source (),//Control. Gbe_mode (1 ' B0),. Sgmii_mode (1 ' B0),//.debug_link_timer_short (1 ' B0),. Force_isolate (1 ' B0),. Forc E_loopback (1 ' B0),. Force_unidir (1 ' B0),////.operational_rate (2 ' B10),. Rx_compensation_err (),. Ctc_drop_flag (),. CTC _add_flag (),. AN_LINK_OK (AN_LINK_OK),//(G) MII TX port.tx_d (Data_buf2chan),. Tx_en (En_buf2chan),. Tx_er (Err_buf2chan),//(G) MII RX port.rx_d (),. RX_DV (),. Rx_er (),. Col (),. CRS (), 8BI TX Port.tx_data (Data_chan2quad),. Tx_kcntl (Kcntl_chan2quad),. Tx_disparity_cntl (Disparity_cntl_chan2quad),// 8BI RX Port.signal_detect (),. SERDES_RECOVERED_CLK (),. Rx_data (),. Rx_kcntl (),. Rx_even (1 ' b0),//signal not used in Norm Al Mode.rx_disp_err (),. Rx_cv_err (),. Rx_err_decode_mode (1 ' b0),//0= Normal Mode, always tie low for SC Familiy.xmit_aut  Oneg (Xmit_autoneg),//Management Interface i/o.mr_adv_ability (+ ' h4001),. mr_an_enable (1 ' B0),. Mr_main_reset (1 ' b0), . Mr_restart_an (1 ' B0),. Mr_an_complete (Mr_an_complete),. Mr_lp_adv_ability (Mr_lp_adv_ability),. MR_PAGE_RX (Mr_page _RX));//Host Bus Register Interface for SGMII IP core//(G) MII rate Resolution for SGMII IP core//QUAD ASB 8B10B + SERDE s////single-ended Crystal PCs u_pcs (//SerDes CLK pins//. Hdoutp_ch0 (Hdoutp0),. Hdoutn_ch0 (Hdoutn0),. Rxiclk_ch0 (),. Txiclk_ch0 (In_ clk_125),. Rx_full_clk_ch0 ( ),. Rx_half_clk_ch0 (),. Tx_full_clk_ch0 (),. Tx_half_clk_ch0 (),. Txdata_ch0 (Data_chan2quad),. Tx_k_ch0 (Kcntl_chan 2quad),. Xmit_ch0 (Xmit_autoneg),. Tx_disp_correct_ch0 (Disparity_cntl_chan2quad),. Rxdata_ch0 (),. Rx_k_ch0 (),. Rx_di Sp_err_ch0 (),. Rx_cv_err_ch0 (),. Sb_felb_ch0_c (1 ' B0),. Sb_felb_rst_ch0_c (1 ' B0),. Tx_pwrup_ch0_c (1 ' B1),. Rx_pwrup_   Ch0_c (1 ' B1),. rx_los_low_ch0_s (),. lsm_status_ch0_s (),. rx_cdr_lol_ch0_s (),. Tx_pcs_rst_ch0_c (Tx_pcs_rst), . Rst_qd_c (Quad_rst),/////misc FPGA_TXREFCLK (in_clk_125),. Tx_serdes_rst_c (1 ' b0),///quad_rst. tx_pll_lol_qd                _s (Tx_pll_lol),. Serdes_rst_qd_c (1 ' b0)),/*pcs_top u_pcs (. RSTN (Rst_n),//refclkp,// REFCLKN,. Txdata_ch0 (Data_chan2quad),. Tx_k_ch0 (Kcntl_chan2quad),. Hdoutp_ch0 (HDOUTP0),. Hdoutn_ch0 (Hdoutn0),. Clk_pcs (in_clk_125)); */endmodule

The above is the code that TOP_HB.V this file. Hope to be useful to everyone.

Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.

Debug lattice debugging of the sgmii.