Debug the SRAM of diy_de2

Two 256kx16bit SRAM memory is used in diy_de2. The read and write operations of SRAM are relatively simple. The operations can be divided into hardware debugging and software debugging.

Debugging environment: Quartus II 9.0 + niosii 9.0

1. hardware debugging

That is to say, the simplest way to read and write the SRAM is to build the SRAM project and read the SRAM project respectively. First, write the SRAM. when the power is continuously on, read the SRAM. Finally, use SignalTap II to observe the value on the data line. This methodProgramIt is relatively simple, but the operation is a little more complicated.

Write Program:

module sram_hr (// host data
clock_50,
led,
/SRAM
sram1_d,
sram1_a,
sram1_ub,
sram1_lb,
sram1_we,
sram1_ce,
sram1_oe
);
// host side
input clock_50;
// SRAM side
inout [] sram1_d;
output [] sram1_a;
output sram1_ub,
sram1_lb,
sram1_we,
sram1_ce,
sram1_oe;
output Reg [] led;
Reg [15: 0] idata;
Reg [17: 0] iaddr;

Wire [15:0] odata;
Reg iwe_n;
Wire ioe_n;
Wire ice_n, iclk;
Wire [1:0] ibe_n;

Assign sramaded = sramadewe? 16 'hzzzz: idata;
Assign odata = sram1_d;
Assign sram1_a = iaddr;
Assign sram1_we = iwe_n;
Assign sram1_oe = ioe_n;
Assign sram1_ce = ice_n;
Assign sram1_ub = ibe_n [1];
Assign sram1_lb = ibe_n [0];

Assign ibe_n = 2' B00;
Assign ice_n = 1' B0;
Assign ioe_n = 1' B0;

Always @ (posedge clock_50)
Begin
Iwe_n <= 1' B0; // we signal low, write SRAM
Idata <= 16 'hffaa; // send the value to be written to the data register. The minimum 4 bits is 4'h5 (or 4' b0101 ),

// Therefore, the minimum 4 bits written into the SRAM data line are sram_dq [3] = 0; sram_dq [2] = 1; // sram_dq [1] = 0; sram_dq [0] = 1;

Iaddr <= 18 'h00001; // address to write
// Led <= odata [7: 0];
End

Endmodule

Read program:

module sram_hr (// host data
clock_50,
led,
/SRAM
sram1_d,
sram1_a,
sram1_ub,
sram1_lb,
sram1_we,
sram1_ce,
sram1_oe
);
// host side
input clock_50;
// SRAM side
inout [] sram1_d;
output [] sram1_a;
output sram1_ub,
sram1_lb,
sram1_we,
sram1_ce,
sram1_oe;
output Reg [] led;
Reg [15: 0] idata;
Reg [17: 0] iaddr;

Wire [15:0] odata;
Reg iwe_n;
Wire ioe_n;
Wire ice_n, iclk;
Wire [1:0] ibe_n;

Assign sramaded = sramadewe? 16 'hzzzz: idata;
Assign odata = sram1_d;
Assign sram1_a = iaddr;
Assign sram1_we = iwe_n;
Assign sram1_oe = ioe_n;
Assign sram1_ce = ice_n;
Assign sram1_ub = ibe_n [1];
Assign sram1_lb = ibe_n [0];

Assign ibe_n = 2' B00;
Assign ice_n = 1' B0;
Assign ioe_n = 1' B0;

Always @ (posedge clock_50)
Begin
Iwe_n <= 1' B1; // we signal low, write SRAM
// Idata <= 16 'hffaa; // send the value to be written to the data register. The minimum value is 4'h5 (or 4' b0101 ),

// Therefore, the minimum 4 bits written into the SRAM data line are sram_dq [3] = 0; sram_dq [2] = 1; // sram_dq [1] = 0; sram_dq [0] = 1;

Iaddr <= 18 'h00001; // address to write
Led <= odata [7: 0];
End

Endmodule

The above is the read/write SRAM, And the read value is assigned to the LED. In addition, you can use the built-in simulation tool SignalTap II in Quartus II to observe the data on the SRAM data bus.

 

2. Software Debugging

This refers to the test of SRAM by using the niosii soft core. There are two methods:

1. Download the soft core to the SRAM. If it can be downloaded and the program runs normally, the SRAM will be normal;

2. Download the soft core to other memory to perform read and write operations on the SRAM. If the read and write data is normal, the SRAM is normal.

 

PS: Both hardware debugging and software debugging projects have uploaded attachments.