Dedicated audio/video protocol-I2C bus protocol

Since the use of computers and networks, it has greatly changed our world. So far, the intelligent brain of chips and hardware devices has been applied and developed in more and more fields. As for protocol, there are also many changes. Next we will introduce the I2C bus protocol for audio and video devices.

I2C bus Definition

The I2C (Inter-Integrated Circuit) bus is a two-line serial bus developed by PHILIPS to connect the microcontroller and its peripheral devices. The I2C bus was originally developed for audio and video devices in 1980s and is now mainly used in server management, including communication in the status of a single component. For example, the administrator can query each component to manage system configurations or master the functional status of the component, such as power supply and system fan. Multiple parameters such as memory, hard disk, network, and system temperature can be monitored at any time, which increases system security and facilitates management.

I2C bus features

The main advantage of I2C bus is its simplicity and effectiveness. Because the interface is directly on the component, the space occupied by the I2C bus is very small, which reduces the space of the circuit board and the number of chip pins, and reduces the interconnection cost. The bus can be up to 25 feet in length and support 40 components at a maximum transmission rate of 10 Kbps. Another advantage of the I2C bus is that it supports multimastering, in which any device capable of sending and receiving can become the master bus. A master can control signal transmission and clock frequency. Of course, there can only be one master at any time point.

Bus composition and signal type

The I2C bus is a serial bus consisting of the SDA data line and the clock SCL, which can send and receive data. Two-way transmission is performed between the CPU and the Controlled IC, and between the IC and IC. The maximum transmission rate is 100 kbps. Various controlled Circuits are connected in parallel on this bus, but just like telephones, only dialing their respective numbers can work. Therefore, each circuit and module has a unique address, in the process of information transmission, each module circuit connected to the I2C bus is both the master controller or the Controller) and the transmitter or receiver), depending on the functions it wants to accomplish. The control signal sent by the CPU is divided into address code and control amount. The address code is used for site selection, that is, the circuit to be controlled is connected to determine the type of control. The control quantity determines the adjusted category, such as contrast and brightness) and the amount to be adjusted. In this way, although each control circuit is mounted on the same bus, it is independent of each other and irrelevant to each other.

The I2C bus protocol specifies three types of signals during data transmission: start signal, end signal, and response signal.

Start signal: in high-power mode, SDA switches from high level to low level to start transmitting data.

End signal: in high-power mode, SDA changes from low-level to high-level and ends data transmission.

Response signal: After receiving 8-bit data, the IC that receives the data sends a specific low-level pulse to the IC that sends the data, indicating that the data has been received. After the CPU sends a signal to the controlled unit, it waits for the controlled unit to send a response signal. After the CPU receives the response signal, it determines whether to continue to transmit the signal based on the actual situation. If no response signal is received, it is determined that the controlled unit has a fault.

Among these signals, the start signal is required. Either the end signal or the response signal can be used.

At present, many semiconductor integrated circuits have integrated I2C interfaces. Single-Chip Microcomputer with I2C interfaces include: CYGNAL's C8051F0XX series, PHILIPSP87LPC7XX series, and MICROCHIP's PIC16C6XX series. Many peripheral devices, such as memory and monitoring chips, also provide I2C interfaces.

I2C bus is a two-way two-wire bus used for the connection between IC Devices. It can be attached to multiple devices and connected through two wires, which occupies a very small space, the length of the bus can be up to 25 feet, and the maximum transmission rate of 10 Kbps can support four components. Its other advantage is the multi-controller, as long as the devices that can receive and send can become the master controller, of course, multiple masters cannot work at the same time.

I2C bus has two signal lines, one of which is an SDA data line) and the other is an SCL clock line ). Clock signals are generated by the master device at any time.

I2C bus protocol operations

I2C procedures use Master/Slave bidirectional communication. When a device sends data to the bus, it is defined as a sender, and the device receives data as a receiver. Both the master and slave devices can work in the receiving and sending status. The bus must be controlled by the main device, which is usually a microcontroller. The main device generates a serial clock-internal clock (SCL) to control the transmission direction of the bus and generate the start and stop conditions. The data status on the SDA line can be changed only during the period when the SCL is low. During the period when the SCL is high, the SDA status change is used to indicate the start and stop conditions.

Control byte

After the start condition, it must be the control byte of the device. The four-bit high is the device type identifier. Different chip types are defined. The EEPROM should generally be 1010 ), the three digits are selected as slices, and the last digit is the read/write bit. When the value is 1, the read operation is performed, and when the value is 0, the write operation is performed.

Write operation

Write operations are divided into two types: byte write and page write. page write operations vary depending on the bytes loaded at a time on the chip.
 
Read operations

There are three basic read operations: Current address read, random read, and sequential read. Figure 4 shows the sequence of sequential reads. It should be noted that the 9th clock cycles of the last read operation are not "irrelevant ". To end the read operation, the host must issue a stop condition between 9th cycles or maintain SDA as high within 9th clock cycles, and then issue a stop condition.