Deep description of selectio in spartan6 series and introduction to advanced applications

1. What is I/O tile?

For the Spartan-6 series FPGA, an I/O tile includes two iob, two ilogic, two ologic, and two iodelay.

 

 

Figure 1 Structure of spartan-6 series I/O tile

 

Figure 2spartan-6 fpga I/O banks

1.1. iob structure introduction

Each iob contains an input, output, and three-state drive. These drivers can be configured with different levels, such as lvttl and lvcmos. Differential Io uses two iobs in one Io tile.

Each iob is directly connected to ilogic and ologic. ilogic and ologic can be configured as iserdes or oserdes ,.

 

Figure 3 structure of basic iob

1.1.1. iob internal terminal Resistance

The use of high-speed IO level standards can optimize the level conversion characteristics and signal integrity. In high-speed IO level standards, terminal resistance is often required. The closer the terminal resistor is to the receiver, the better.

Spartan-6 FPGA provides in-chip terminal resistors for differential Io and single-ended Io, which are located inside iob. Using these terminal resistors can prevent FPGA from being reconnected to the external pins.

• Terminal resistance of differential Io

The Spartan-6 series provides a terminal resistance of 100 Ω for differential Io. The terminal resistance of the differential pin can be enabled or disabled through the constraint file.

 

Figure 4 differential pin enable terminal Resistance

 

Figure 5 Non-enable terminal resistance on the differential pin

• Single-ended terminal Resistance

Both the input terminal resistance and output impedance of the single-ended pin are programmable, as shown in figure: the FPGA output on the left enables the output impedance of 50Ω, the FPGA on the right enables the input of 50% Partial voltage resistance; in high-speed interface applications, enabling the output impedance can reduce electromagnetic reflection, the available output impedance values of the Spartan-6 series FPGA are none, 25Ω, 50Ω, and 75Ω. The input impedance can be set to 25%, 50%, or 75% partial pressure.

 

 

Figure 6 one-way SSTL interface using on-chip terminal Resistance

1.1.2. Java primitive that can be instantiated in iob

Iob has a variety of buffer resources, which can be called in the form of primitives. In the Spartan-6 series, the single-ended Io standard primitives are as follows:

Primitive	Function
Ibuf	Input buffer
Ibufg	Clock input buffer
Obuf	Output buffer
Obuft	Output three-state Buffer
Iobuf	Input/output buffer

At the same time, there are 7 differential Io standard primitives

Primitive	Function
Ibufds	Input buffer
Ibufgds	Clock input buffer
Ibufds_diff_out	Anti-output buffer
Ibufgds_diff_out	Clock anti-output buffer
Obufds	Output buffer
Obuftds	Three-state output buffer
Iobufds	Input/output buffer

 

1.1.3. iob standard for available I/O Levels

Iob supports a variety of level standards, allowing you to flexibly select the appropriate Io level standards for your own design. The IO level standards supported by the Spartan-6 series are as follows:

 

 

Standard	Explanation	Purpose and vendor	Input buffer	Output buffer
Single-ended Io level standard
Lvttl	Low Voltage TTL	General Purpose 3.3 V	Lvttl	Push-pull
Lvcmos	Low Voltage CMOS	General Purpose	CMOS	Push-pull
PCI	Peripheral Component Interconnect	PCI Bus	Lvttl	Push-pull
I2C	Inter integrated Circuit	NXP	CMOS	Open drain
SMBus	System Management Bus	Intel	CMOS	Open drain
Sdio	Secure Digital Input Output	SD card assoc, Memory card	CMOS	Push-pull
Mobile DDR	Low Power DDR		CMOS	Push-pull
HSTL	High-speed Transceiver Logic	Hitachi SRAM; IBM; Three of four classes Supported	Vref based	Push-pull
Hstl18	High-speed Transceiver Logic	Hitachi SRAM; IBM; Three of four classes Supported	Vref based	Push-pull
Sstl3	Stub Series Terminated logic 3.3 V	SDRAM bus; Hitachi And IBM; two classes	Vref based	Push-pull
Sstl2	SSTL for 2.5 V	DDR SDRAM	Vref based	Push-pull
Sstl18	SSTL for 1.8 V	DDR SDRAM	Vref based	Push-pull
Sstl15	SSTL for 1.5 V	DDR SDRAM	Vref based	Push-pull
Differential Io level standard
Lvds25 Lvds33	Low Voltage Differential Signaling	High-speed Interface, backplane, Video; national, Ti	Differential Pair	Differential Pair
Blvds	Bus LVDS	Bidirectional, Multipoint LVDS	Differential Pair	Pseudo Differential Pair
Display Port	Auxiliary Channel Interface for display Port	Flat panel displays	Differential Pair	Pseudo Differential Pair
Lvpecl	Low voltage positive ECL	High-speed clocks	Differential Pair	N/
Mini_lvds	Mini-LVDS	Flat panel displays	Differential Pair	Differential Pair
RSDs	Reduced swing Differential Signaling	Flat panel displays	Differential Pair	Differential Pair
Tmds	Transition minimized Differential Signaling	Silicon image; DVI/HDMI	Differential Pair	Differential Pair
PPPs	Point-to-Point Differential Signaling	LCDs	Differential Pair	Differential Pair
Differential Mobile DDR	Differential lpddr For CK/ck #		Differential Pair	Pseudo Differential Pair
Diff_hstl_ I Diff_hstl_iii Diff_hstl_iv Diff_hstl_ I _18 Diff_hstl_iii_18 Diff_hstl_iv_18	Pseudo differential HSTL	SRAM	Differential Pair	Pseudo Differential Pair
Diff_sstl3_ I Diff_sstl3_ii Diff_sstl2_ I Diff_sstl2_ii Diff_sstl18_ I Diff_sstl18_ii Diff_sstl15_ii	Pseudo differential SSTL	DDR, DDR2, Ddr3 SDRAM	Differential Pair	Pseudo Differential Pair

 

 

1.1.4. Unused pin status after FPGA Configuration

By default, after the FPGA configuration is complete, all unused pins are configured as inputs and are grounded by a drop-down resistor inside the iob, you can use unusedpin bitgen option to set the status of unused pins after configuration.

1.2. selectio logical resources

The logical resources of selectio include basic resources and advanced resources. The basic resources include:

• Combinatorial input/output, combined input/output
• 3-state output control, three-state output control
• Registered input/output, register Input and Output
• Registered 3-state output control, register three-state output control
• Double data rate (DDR) input/output, double data rate input/output
• DDR output 3-state control, double data rate three-state output control

Advanced resources include:

• Iodelay2, which provides users with precise latency Control
• None, C0, and C1 output DDR mode, output double data output
• None, C0, and C1 input DDR mode, double data input
• Iserdes, input string and convert
• Oserdes, output and String Conversion

 

Selection logical resources are combined in an IO tile, as shown in. In single-ended mode, Master I/O buffer drives P pad and slave I/O buffer drives n pad; in the differential mode, the master I/O buffer and slave I/O buffer can be combined to complete serial concatenation or String Conversion.

 

Figure 7 selectio logical resources in an I/otile

 

1.3. Available clock resources in selection resources

An internal SDR clock is required for all Io data collection and conversion (including string-to-String Conversion and parallel String Conversion) and DDR transmission. To implement these functions, the I/O interface tile requires a local clock multiplier to obtain the SDR clock.

The frequency multiplier for DDR transmission requires two input clocks, which must be one of the following three cases:

• A global clock and its local (in the I/O interface resource) Get the reverse clock
• Global clock with a phase difference of 180 °
• I/O clock with a phase difference of 180 °

 

Figure 8io interface logical clock Resource

 

Deep description of selectio in spartan6 series and introduction to advanced applications