Deep understanding of the ARM Embedded System guiding process-based on at91sam9261 microprocessor and realview tool chain

Deep understanding of the ARM Embedded System guiding process-based on at91sam9261 microprocessor and realview tool chain

Understanding the boot process of ARM embedded system-based on the at91sam9261 micro processor and realview toolchain

For ARM embedded applications without Operating SystemsProgramIn this way, we can understand the guiding process. It begins with the main function after the system is powered on. Although the guiding details of different applications vary, in general, key peripheral devices are initialized, Memory re- ing is executed, and memory layout is arranged. This article first introduces some key concepts, and then describes the entire guidance process of the ARM embedded system starting from the first command executed by the system on power. The main board of the example program running in this article is based on the AT91SAM9261-EK evaluation board of ATMEL Corporation, extended a piece of ncs0, the address is 0x10000000, the size is 4 MB byte norflash, And the BMS pin grounding, in this way, the external norflash boot is automatically extended after the system is powered on. The integrated development environment is μvision3. 62c of Keil, And the realview toolchain is configured.

1 key concepts 1.1 memory ing

For any type of memory, you must first allocate an address space for it to access it. In this way, a corresponding relationship is established between the address space and the memory, called memory ing. Whether the microprocessor's built-in in-chip memory or the extended external memory, after the circuit board is created, its memory ing is naturally fixed, this specific address space is also known as its inherent address space. For example, for at91sam9261, the address space 0x30,000 0-0x40, 0000 is mapped to the on-chip SRAM, that is, the inherent address space of the On-Chip SRAM is 0x30,000 0-0x40, 0000.

1.2 memory re ing

For arm processors, a specific address space can be mapped to a different memory to obtain multiple boot options or improve performance. Alternatively, a memory can correspond to multiple address spaces, this phenomenon is called memory re ing. For example, at91sam9261 does not have an address space 0x0-0xf. FFFF arranges inherent memory ing based on the status of the BMS pin at power-on, or you can program the matrix_mcfg register to map different memory to 0x0-0xf, FFFF, as shown in 1, it is precisely for this reason that this address space is also called the boot memory, or the re ing area. In this article, the BMS pin is grounded. After the system is powered on, norflash returns 0x0. In addition to its inherent memory ing 0x1000,000 0, you can also access it through its re ing address 0x0. If the on-chip SRAM is re-reflected to the address 0x0, and then the access address 0x0, the actual access is the on-chip SRAM.

Figure 1 re ing

In short, from the perspective of address space, the memory ing corresponding to this special re ing area has multiple and temporary features, but its memory ing is unique at any time. In addition to this special re ing area, other address spaces and storage space correspond one-to-one. On the contrary, from the memory perspective, it can always be accessed through its inherent address space at any time, but it can be accessed from the re ing region only when certain conditions are met.

2 storage layout

The realview toolchain uses the distributed loading mechanism to create complex image files. The distributed file can accurately describe the loading and execution views of each area in the image. Load view description the memory layout before the image starts execution, and execute view description the memory layout when the image is executed. The smallest unit that can be described by a distributed file. the area in the s file, such as cstartup and vector in board_cstartup_keil.s. c files, such as board_lowlevel.c and board_memories.c.

The Distributed File norflash. SCT used in this article is as follows. It can be seen that there is only one loading area named load_region, that is, the image file is stored in the norflash address 0x0000000; there are four execution areas, fixed_region (including cstartup region and most sections with Ro attributes), relocate_region (including exception vectors and board-Level Initialization)CodeThe object files generated after compilation and the sections whose attributes are RW and Zi), arm_lib_heap (HEAP), and arm_lib_stack (from the top of the SRAM in the chip to the stack area that begins to grow down ).

Load_region 0x10000000 0x400000 {

Fixed_region 0x10000000 {

* (Cstartup + first)

. Any (+ RO)

}

Relocate_region 0x300000 0x28000 {

*. O (vector, + first)

Board_lowlevel.o (+ RO)

Board_memories.o (+ RO)

. Any (+ RW + zi)

}

Arm_lib_heap 0x326000 empty 0x1000 {

}

Arm_lib_stack 0x328000 empty-0x1000 {

}

}

3. system initialization 3.1 First Command

The ARM core always extracts the first instruction from address 0x0 and starts the boot process. In this article, the image file is burned to norflash. In order to boot from norflash, the BMS pin is grounded. In this way, the norflash returns to the address 0x0. The code for cstartup is as follows:

Area cstartup, code

Entry

Resethandler

; The first instruction set PC to actual code location (I. e. Not in remap zone)

Ldr pc, = label

Label

LDR r0, = | image $ arm_lib_stack $ Zi $ limit |

MoV sp, R0

; Other codes

Because the cstartup area is located at the starting position of norflash, the First Command executed is ldr pc, = label. This is a pseudo command. The assembler places the label value in a literal pool and generates a LDR command for PC addressing to load the value from the pool. This can be confirmed from the output of the. axf file generated by IDA-the interactive disassembler disassembly:

0x10000000 ldr pc, [PC, #0x34]; 34 F0 9f E5

...

0x1000003c DCD 0x10000004

We can see that the label value is equal to 0x10000004, which is stored at the address 0x1000003c. The first instruction is encoded as 34 F0 9f E5, that is, ldr pc, [PC, #0x34]. After executing this instruction, PC = PC + 0x8 + 0x34 = PC + 0x3c, obtain the value at 0x3c offset from the current command address (0x10000004) and assign it to the PC register, that is, jump to the absolute address 0x0000004 and continue execution. The subsequent two Assembly statements set a temporary stack to prepare for calling the function lowlevelinit written in C language.

3.2 key peripheral devices

During system boot, key peripheral devices such as crystal oscillator and Phase Lock Loop, advanced interrupt controller, and watchdog must be initialized. They are all completed in the lowlevelinit function. The peripheral initialization codes of different applications vary greatly, so we will not detail them here.

3.3 re-map exception vectors and exception Processors

All arm systems have a vector table at address 0x0. Although the vector table is not part of the initialization sequence, it must exist. It is a jump instruction table to each abnormal processor. When an exception occurs (for example, data abort, undefined command, IRQ, etc.), the ARM core immediately extracts one of the eight commands between the address 0x0 and 0x1 and executes it. If the program does not need to handle this exception, you can place an infinite loop, for example:

Undefvector

B undefvector

If you must handle this exception, such as a reset exception, you can place a jump command relative to the PC, for example:

Ldr pc, = resethandler

Obviously, the current memory layout cannot meet this requirement, because address 0x0-0xf and FFFF are mapped to norflash at this time, and the starting position of norflash is the cstartup region, rather than the exception vector. To meet the arm's need to check the location of the exception vector, the next step in the pilot process is to reapply the on-chip SRAM to 0x0-0xf and FFFF, which is done by calling the board_remapram function. Note: At this time, the exception vector is not actually ready. The exception vector can be accessed only after the vector region is copied from the loading zone to the starting position of the in-chip SRAM using the distributed loading mechanism.

Finally, call the board_configurenorflash function to configure the External Bus Interface and select 0 (EBI CS0). Because the default configuration parameters are not optimal, You need to reconfigure them based on the memory features.

3.4 set stacks in various modes

The stack of the ARM processor has two main features, one of which has its own stack pointer sp, and the other has a decreasing stack. The setting method is to enter various modes in sequence and assign the correct value to the SP. Generally, the supervisor and user mode have the largest stack, followed by the IRQ and FIQ modes. In other modes, only a few bytes are required. In this article, first set the IRQ mode stack to the top of the On-Chip SRAM, then set the stack in the supervisor mode, and enable both IRQ and FIQ.

3.5 from loading view to execution View

When the linker generates an executable image, it also defines the corresponding absolute addresses in the image. The application can run normally only by moving them to the corresponding address. The read-write RW section is used as an example. If the value is not moved from the flash memory to the read-write RAM memory before it is rewritten, an exception will inevitably occur.

The _ main routine in the arm library is responsible for converting the loading view into the execution view, and finally calling the main function written in C language. The _ main routine has three main functions: copy the zone to be moved, zero-initialization Zi zone, and initialization stack and heap, which correspond to ① ③ In Figure 2 respectively.

The sections of most Ro attributes are located in norflash. The starting address of the loading view and execution view is the same, so you do not need to move them.

The loading view in the relocate_region area is different from the starting address of the execution view, so you need to move it. Location of the vector segment to the in-chip SRAM is mainly to meet the ARM architecture's location requirements for the exception vector, after executing the SRAM re ing in the initialization sequence, you can access the exception vector at address 0x0. Board_lowlevel.o and board_memories.o follow the vector, and they are located in-chip SRAM to improve system performance.

Last, place the section with the attribute Zi. The Zi section does not occupy space in the image. They are created and initialized in the SRAM.

The arm_lib_stack execution zone is used to allocate stack space for various modes. It is from the top of the SRAM, that is, the address 0x328000, and starts to grow downward. The execution zone of arm_lib_heap, that is, the heap space. It increases from the address 0x326000.

Figure 2 from loading view to execution View

3.5 main debut

The _ main routine finally calls the main function written in C language after the task is completed. The guiding process ends and the user program starts to execute.

References

[1] Andrew N. sloss, Dominic Symes, Chris Wright. ARM Embedded System Development: Software Design and Optimization [M]. translated by Shen Jianhua. beijing: Beijing University of Aeronautics and Astronautics Press, 2005.

[2] Randal E. Bryant, Davido 'hallaron. Have an in-depth understanding of computer systems [M]. Dr. Li, Lei Yingchun, translated. Revised version. Beijing: China Power Press, 2004.

[3] David seal. Arm Architecture Reference Manual (2nd edition) [M]. Addison-Wesley, 2001.

[4] Getting started with the at91sam9261 microcontroller [Eb/Ol]. http://www.atmel.com/dyn/resources/prod_documents/doc6298.pdf

[5] John R. Levine. linkers and loaders [M]. Morgan Kaufmann, 1999.

Note:Source codeHttp://files.cnblogs.com/dreamliner/getting-started-project-at91sam9261-ek.rar