Design and Implementation of FPGA-based Ethernet MII interface Extension

Abstract: This article introduces the hardware implementation method of Ethernet MII Interface Based on FPGA and extended functions. The hardware structure consists of the control signal module, divider, asynchronous FIFO buffer, and 4b/5b encoding.

Key words: M Ethernet MII; FPGA; Parity divider; 4b/5b codec; asynchronous dual-port FIFO

Introduction

Traditional PC-centered Internet applications have now begun to focus on embedded devices. According to predictions from network experts, 70% of the information transmitted over the Internet will come from small embedded systems. Therefore, it is necessary to study the access of embedded systems to the Internet. At present, there are two ways to achieve single-chip microcomputer system access to the Internet: one is to use NIC (network control/NIC) to achieve network interface, the single-chip microcomputer to provide the required network protocol; another method is to use a chip with a network protocol stack structure and a PHY (Physical Layer receiver) to implement network interfaces, the master controller is only responsible for placing appropriate data in a register of the protocol stack structure chip. At the same time, the use of FPGA to achieve single-chip microcomputer system access to the Internet has been increasingly valued. In this paper, FPGA is used to implement the network protocol stack, and the hardware implementation method of M Ethernet MII interface protocol is introduced. Common devices such as parity module divider and asynchronous FIFO are also very useful in daily use.

 

In the standard series of Ethernet MII Interface Protocol IEEE802, the data link layer includes the LLC (Logical Link Control) Sub-layer and MAC (Media Access Control) Sub-layer. Mac acts as a child layer to encapsulate, unseal, send, and receive data frames. The structure of the physical layer PHY varies with the transmission rate. In M and M Ethernet, the PCs sub-layer, PMA sub-layer, and PMD sub-layer are arranged in sequence. The MII interface is the interface connecting the data link layer and the physical layer. Because the Ethernet speed is 100 Mb/s in this design, the MII interface is actually connected to the MAC Sub-layer and PCs sub-layer. According to the Protocol, the MII interface has the following functions: Data and frame separator read/write clock synchronization, providing independent read/write data channels, providing corresponding management signals for the MAC layer and PCs layer, and supports full duplex mode.? Extension of the MII Interface Function and Its FPGA implementation because the M Ethernet physical layer adopts 4b/5b encoding, in order to expand the MII interface function, it is required to implement direct transfer and transfer of 5-bit data on the physical layer and 8-bit data on the MAC layer. That is, the data used for sending from the MAC Sub-layer and the data used for receiving from the PHY are stored in the data buffer FIFO. At the same time, the MII interface is required to convert the signals Col, CRS from the PHY into the signals carrier and collision, it is also provided to the Mac sublayer for carrier monitoring and conflict detection, as well as transmission of clock, enable, and error bit signals during sending and receiving. As shown in figure 1, the extended MII interface consists of four modules: 4b/5b ***, control signal and 4-bit/8-bit conversion, divider, and dual-port FIFO, it also supports both half-duplex and full-duplex modes. In the design process, in order to consider the need to test and support multiple transmission rates, it is required to design a parity-based divider with a frequency-division parameter, and support a FIFO that can simultaneously perform read/write operations and asynchronous read/write clock. This is a difficult point in the design of the MII interface, and it also has a high practical value.? The realization of the parity divider is the basic circuit in the design of the digital system. In the same design, multiple forms of Frequency Division are sometimes required. Generally, the counter or counter cascade forms the even division and the odd division of non-equal duty cycle, which is easy to implement. The odd division of equal duty cycle is more difficult to implement. In this paper, the basic idea of dividing the 2n + 1 duty cycle by odd number is: first, the 2n + 1 counter is used to realize the odd frequency division with the duty cycle of N + 1/N (for example, tri-frequency, the duty cycle of the positive and negative waveforms is), and there are two ways to achieve the odd division of the duty cycle. One is when the counter reaches n + 1, make the waveform and the input clock waveform "and", but there may be glitch output; the other is when the counter reaches n + 1, A low-level pulse is triggered along the descent edge of the input clock and then "or" is in phase with the original waveform. This method is not produced by glitch. Therefore, this article uses the second method.? 4b/5b encoding ** is designed to reduce system overhead. This article focuses the coding and decoding of 4b/5b on a single module at the same time. DATA 0 ~ F can be directly edited and decoded. The PCS layer has six special 5B codes: 11111 indicates the padding code between frames; 11000, 10001, 01101, and 00111 are two pairs of paired code groups, they are the delimiters at the beginning and end of the data stream, and 00100 is the data error bit used to indicate errors. When receiving data, you can directly decode these 5B code groups, and 00100 generates the signal rx_er. When sending, You need to determine the signal bit sent from the MII interface: If tx_en is on the rising edge, the SSD will be encoded when the first two leading codes are on. If tx_en is on the falling edge (frame interval ), the ESD is output after the FCS, and the code is always filled with 11111 for the data stream interval. If tx_er is triggered, the Code 00100 is output.? Asynchronous dual-port FIFO is designed to meet the requirements of physical layer clock and MAC layer bus clock synchronization of PCs layer data. FIFO requires asynchronous read and write clock. When the conflict detection col is high, it is required to send frames and perform the return operation back to the FIFO to wait for the next transmitting signal. The design idea of FIFO is as follows: Set Asynchronous Reset, triggered at a high level; set the 8-bit register prepare odata to save the FIFO data; Set export o_rp and export o_wp to read and write pointers; cr_rp and cr_wr to carry signs, when export o_rp and export o_wp are FIFO_DEPTH-1, take the inverse; Set nempty, nfull, near_empty, near_full is empty data, full indication.

When the primary o_rd is 1, then primary o_out <= primary odata [primary o_rp], primary o_rp <= primary ORP + 1; Primary o_wr is 1, then primary odata [primary o_wr] <= primary o_in, export o_wr <= export o_wr + 1. The changes in nempty and nfull bit signal values are determined by the carry output of r_rp and cr_wr. When the Read and Write pointer values are equal, that is, when the export o_rp = export o_wp, judge the cr_rp ^ cr_wr (exclusive or) value: If it is 1, the FIFO is full, nfull <= 0; if it is 0, the FIFO is null, nempty <= 0. If fifo_rp! = Export o_wp, then nfull = nempty = 0, FIFO is neither empty nor full. During the test, the tentative capacity of fifo_depth is 32 (the actual requirement is that the size of at least one frame is 1530 bytes), and the Read and Write clocks are 50 MHz and 25 MHz respectively, read and Write simultaneously after writing 550ns.

The implementation of the main control module requires the following functions: 4/8-bit data conversion; control signal output to the MAC layer and PCs layer; two-way data mdio, it represents the connection between the MII interface and the physical layer, and supports asynchronous input/output control.

The requirements for 4/8-bit data conversion are as follows: During sending, 8-bit data is divided into two nibble data for output in sequence; During receiving, fill in the 4-bit data received by 4b/5b encoding *** in order to form an 8-bit data output consisting of high and low nibble.

The output of control signals using status registers is the core of the MII module. Set up three status1 [], from high to low is {duplex, Col, CRS} input; four status2 [], from high to low is {transmitting, transmiterror, rx_en, rx_er. The basic algorithm flow for outputting control signals is as follows:

. Status1 [2] is 1, and works in full duplex mode. The collisiondetect and carriersense outputs are always set to 0.

When status1 [2] is 0, it works in half duplex mode. If status1 [1] is 1, The collisiondetect output is set to 1 and the return program (backoff) is started. If status1 [0] is 1, The carriersense output is set to 1, wait.

When status2 [1] is 1, the job is in the receiving status, and the processing output is set to 1 (status2 [3] Must be 0 at this time ). In this case, if status2 [0] is 0, the received data is valid, and the receivedatavalid output is 1. Otherwise, it is set to 0 to stop data transmission.

When the value of. status2 [1] is 0, the task is in the stopped receiving State, and the output of processing is set to 0. In this case, if status2 [0] is 1 and eceivedatavalid is output to 0, if the acceptor data is 1110, it indicates a carrier error. If the acceptor data is 0000, it indicates a normal frame interval; if status2 [0] is 0, it indicates the normal frame interval stage, and the receivedatavalid output is 1.

When status2 [3] is 1, the task is in the sending status, and tx_en output is set to 1 (status2 [1] Must be 0 at this time ). In this case, if status2 [2] is 0, the message is sent normally, and tx_er is set to 0; otherwise, the message is sent incorrectly, tx_er is set to 1, and skip this byte to continue executing the sending program.

. When status2 [3] is 0, if status2 [2] is 0, it is in the normal frame interval, and tx_en and tx_er are set to 0. If status2 [2] is 1, it is invalid. In this article, we use the cyclone ep1c20f400c8 chip of altela. The whole design is implemented by using the hardware description language of Tilde, the design, integration, simulation, ing and layout of the entire module are completed on the design platform of quatus4.0. As shown in waveform 3 of the sending time series simulation, when a conflict occurs during transmission, the 32-Bit Blocking code (hexadecimal ff) is sent ), then, the system randomly delays a period of time to re-use the media to transmit data. This indicates that this module meets the Protocol requirements and CSMA/CD. Conclusion This article introduces a simple design method of Ethernet MII protocol based on FPGA. This module can be used to easily implement the Internet interfaces of small embedded systems. If you combine the MAC layer protocol and TCP/IP protocol stack based on FPGA and other auxiliary function modules, this not only simplifies the access to networks for small embedded systems, but also improves the system integration and stability. (Xu junlin aquatic)