Design Concept of FPGA Asynchronous FIFO (2)

Design Concept of FPGA Asynchronous FIFO (2)

First, we will discuss the Gray code encoding method:

 

 

Let's first look at the 4-bit gray code. When MSB is 0, the positive count is displayed. When MSB is 1, that is, the pointer has already passed through, and the highest digit is flipped. At this time, the gray code is counted in reverse order, the entire set of data is symmetric centered on the maximum value (depth), and each number meets the Gray code requirement, that is, the next state changes only 1 bit from the previous state.

3-bit gray code, after the highest bit reversely, that is, the pointer reaches the last address of the FIFO, and starts counting again at the low bit. A problem is that in the place where the highest bit jumps, two Bite data changes, which violates the Gray Code Law.

 

 

The above is a model that uses gray code to generate data pointers. If Gray code is used to transmit FIFO pointer data, the depth of the FIFO must be pow2. in the above model, the pointer PTR first converts the Gray code into binary data through the gray to binary comb logic module, then adds one to get bnext, and then converts bnext to gnext through binary to gray comb logic, then gnext obtains the New Data Pointer PTR through the Register output. then, the addrmsb is calculated based on the highest bit and secondary high bit of gnext.

 

The above is the second Data Pointer generation model. First, after the data address is removed from the highest bit, the pointer is involved in the addition operation to obtain a new data address in binary format.

Then add the new data address obtained by adding one to convert the Gray code to get the value of gnext, and then output the Data Pointer (using the gray code) through the Register) and the data address value (in binary format ).

 

The above is an overall design model of FIFO.

 

In actual operation, the problem of generating a null full flag signal

 

Needless to say about the specific logic

 

When generating empty signals, the highest bit and the data address are completely equal, it can be determined to be empty.

The generation of full signals is more complex:

 

If the previous judgment basis is used, the highest bit of the pointer is different, and the rest of the data addresses are identical, if the Gray code encoding method is used, problems will occur.

 

The basis for determining the full signal indicates that the maximum two digits of the read pointer and the write pointer are different at the same time, and the rest is the same, that is, the first half of the first half is full.

 

Design Concept of FPGA Asynchronous FIFO (2)