Design of an even, odd, half integer divider and any divider based on Verilog

In the learning process of FPGA, the simplest and most basic experiment should be the crossover device. Because the crystal frequency of the FPGA is fixed value, can only produce a fixed frequency timing signal, but the actual project we need a variety of different frequency signals, this time we need to the frequency of crystal oscillator to divide. For example, if the FPGA chip crystal frequency is 50MHz, and we want to get 1MHz square wave signal, then the crystal oscillator will need to generate 50 of the signal.

Although the design of the crossover is the simplest experiment in the FPGA learning process, it takes a lot of effort to really figure out the ins and outs of the crossover. Here are some of the most common types of dividers:

1. Even divider

I believe that most of the friends in the study of FPGA in the process of exposure to the first experiment should be even the frequency divider, even the design of the more simple, with a simple counter can be achieved. For example, to achieve an n-frequency (n-even) divider, you can write a counter, when the count to (n/2-1), let the output state flip, and the counter is zeroed, so that the output signal is the input clock of the N-frequency. The specific code is as follows:

Even divider example, 20-n=20, duty-free 50%

ModuleClk_div (Clk_out, CLK, rst_n);inputCLK, Rst_n;Outputclk_out;Regclk_out;Reg[4:0] CNT; always@(PosedgeClassor Negedgerst_n)if(!rst_n)beginCNT<=5'B0;Clk_out <=1'B0;    EndElse if(CNT = =4'D9)    beginCNT<=5'B0;Clk_out <= ~clk_out; EndElseCNT <= CNT +1'B1;Endmodule

2. Odd divider

The odd divider is designed to be more complex than an even divider, especially an odd divider with a duty ratio of 50%. If there is no clear requirement on the duty ratio, you can directly count the rising edge, Count to (N-1)/2 when the output is flipped, count to (N-1) The output state is flipped again, and the counter is zeroed, so that a duty-ratio of 2:3 of the N-divided (n-odd) divider. If you want to achieve a 50% duty ratio, it can be achieved by means of "dislocation phase or". The specific method is to use the first method by the rising edge count to generate a duty ratio is not 50% of the n divider, and then the same method on the falling edge count to produce a duty ratio is not 50% of the N-divider, and finally the output of these two dividers "or" operation, you can get the duty ratio of 50% odd-N divider , the specific implementation code is as follows:

Example of an odd divider, 5-way, duty-free 50%

Modulediv_odd (Clk_out, CLK, rst_n);inputCLK, Rst_n;Outputclk_out;Regclk_p, Clk_n;Reg[4:0] Cnt1, Cnt2;//Note Adjust the bit width according to the actual needparameterN =5;//here n can be set to any odd number//a crossover signal with a non-50% duty ratio is generated by the rising edge clk_p always@(PosedgeClassor Negedgerst_n)if(!rst_n)beginCnt1<=0; Clk_p<=0; EndElse if(Cnt1 = =5'B10)//cnt_p = = (N-1)/2, Flip    beginCnt1<= Cnt1 +1'B1;Clk_p <= ~clk_p; EndElse if(Cnt1 = =5'b100)//cnt_p = = N-1, flip    beginCnt1<=1'B0;Clk_p <= ~clk_p; EndElseCnt1 <= Cnt1 +1'B1;//a crossover signal clk_n with a falling edge to produce a non-50% duty-free ratio always@(NegedgeClassor Negedgerst_n)if(!rst_n)beginCnt2<=0; Clk_n<=0; EndElse if(Cnt2 = =5'B10)//cnt_n = = (N-1)/2, Flip    beginCnt2<= Cnt2 +1'B1;Clk_n <= ~Clk_n; EndElse if(Cnt2 = =5'b100)//cnt_n = = N-1, flip    beginCnt2<=1'B0;Clk_n <= ~Clk_n; EndElseCnt2 <= Cnt2 +1'B1;//Phase operation to get a 50% duty-divided signalAssignClk_out = Clk_p |Clk_n;Endmodule

3. Half-frequency divider (n+0.5)

   In the actual project, we also often encounter the half-frequency converter. For example, to get a 2MHz clock signal, and the system crystal oscillator frequency is 25MHz, this time need to make the system clock 12.5. So how can this half-frequency divider be implemented? The most straightforward way of course is to use the counter, because the half-integer division can not achieve 50% of the duty cycle (because the 50% duty ratio requires a period of high and low levels are 6.25 system clock cycles, this 0.25 is not possible), we can only let the duty ratio as close as 50%. In the case of 12.5, we can count the system clock, output low in the first 6.5-cycle period, output high level after 6 cycles, loop sequentially, can achieve 12.5 divide, the duty cycle is (6.5/12.5), close to 50%. The count involves a 0.5-cycle period, so the rising and falling edges are counted. The specific code is as follows:

Half-frequency divider, take 12.5 divide for example, duty ratio (6.5/12.5)

Moduleclk_half (Clk_out, Clk1, CLK, rst_n);inputClk,rst_n;OutputClk_out,clk1;parameterN = -;//take the 12.5 divide as an example, n=13 WireClk1;Regclk_out;Reg[4:0] CNT;RegFlag =1'B0;//system Clock CLK counter always@(NegedgeClassor Negedgerst_n)if(!rst_n) Flag <=1'B0;Else if(CNT = =5'd6) flag <= ~flag;//flips the CLK1 state immediately after the end of the fifth clockAssignCLK1 = (flag)? ~CLK:CLK;//Clock clk1 counter, modulo n always@(PosedgeClk1or Negedgerst_n)if(!rst_n) CNT <=5'B0;Else if(CNT = =5'D12) CNT <= 5'B0;ElseCNT <= CNT +1'B1;//The first 6.5 cycles are low, the last 6 periods are high,//that is 12.5-frequency always@(PosedgeClk1or Negedgerst_n)if(!rst_n) Clk_out <=1'B0;Else if(CNT = =5'd0) clk_out <= 1'B0;Else if(CNT = =5'd7) clk_out <= 1'B1;ElseClk_out <=clk_out;Endmodule

There are many other half-frequency programs written by other great gods, such as:

Http://www.cnblogs.com/yuzeren48/p/3965003.html

4. Arbitrary crossover--based on the principle of phase accumulation

Phase accumulator is mainly used in direct digital synthesizer (DDS), wherein the main parameters are input frequency FC, output frequency FO, counter bit width n, frequency control word K (i.e. counter increment step). The relationship between them is: fo= (fc*k)/(2^n). Assuming that the input frequency FC is 50MHz, the counter bit width N is 32, to produce a 1kHz signal, then k= (fo*2^n)/fc=85.9*fo=85900. When the count value is less than or equal ((2^n)/2), the output is low and when the count value is greater than ((2^n)/2), the output is high, and in turn, a 1kHz signal with a duty cycle of 50% can be generated. The following procedures can be designed:

Arbitrary crossover example, output 1kHz, duty 50%

/*************************************** Crystal oscillator Frequency FC = 50MHz Output frequency fo = 1kHz (can be set to any value as needed) control parameter K = (fo*2^n)/fc parameter N = 2^32, (32 counts Bit width of the digital device) ****************************************/ModuleDiv_free (Clk_out, CLK, rst_n);inputCLK, Rst_n;Outputclk_out;Regclk_out;Reg[ to:0] CNT; always@(PosedgeAlor Negedgerst_n)if(!rst_n) CNT<=0;ElseCNT <= CNT + +'d85900; Counter Step K always@(PosedgeAlor Negedgerst_n)if(!rst_n)beginClk_out<=1'B0;    EndElse if(CNT < +'h7fff_ffff)Clk_out <=1'B0;ElseClk_out <=1'B1;Endmodule

Design of an even, odd, half integer divider and any divider based on Verilog