Design of High-Speed Data Collection System Based on USB2.0 and FPGA technology

Design of High-Speed Data Collection System Based on USB2.0 and FPGA technology

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Source: Electronic Technology Application Author: Yuan Jiangnan

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In recent years, laptop computers have been rapidly popularized and updated, most of which do not have RS232 interfaces configured, and USB interfaces have become the mainstream of PC and peripheral interfaces in the future. This collection system is designed to build a multi-functional universal data collection and transmission platform based on the USB interface, integrates the real-time and flexibility of embedded systems with the powerful data storage, processing, and display functions of PCs. This collection system has broad application prospects in the fields of Intelligent Instruments, measurement and control systems, and industrial control systems.
1. Overall System Structure Design
1.1 overall System Structure
The system consists of single-chip microcomputer and USB interface module, FPGA module, signal conditioning module, and A/D module. Among them, the peripheral circuit of single chip microcomputer is relatively simple, the whole system is mainly controlled through the PC program interface, the USB interface is responsible for communicating with the PC, and the FPGA module is responsible for data collection and caching.

1.2 single-chip microcomputer and USB interface module
The purpose of this design is to build a data acquisition system with a PC as the platform. The single-chip microcomputer function is limited to receiving PC commands and controlling FPGA work. As the human-machine interface of the entire system, PC controls the entire data collection system for collection, storage and processing. Therefore, the single-chip microcomputer can choose a low-cost 8xc51 series. To improve the system flexibility, a single-chip microcomputer and USB interface chip separation solution were adopted, and Philip's ISP1581 USB interface chip was selected. The interface between this chip and the 8xc51 single-chip microcomputer is very simple and can greatly reduce system costs.
1.3 FPGA module
The most important feature of Sampling Control Using FPGA is that the system is restructured and universal. The design uses the low-cost FPGA cyclone series of Altera (which can also be implemented on cheaper acex1k devices in actual experiments) to control high-speed A/D chips to sample at a speed of 20 Msps. The Design of FPGA module includes FIFO, single-chip microcomputer interface, A/D control interface, DMA control module, master controller, and other sub-modules.
1.4 PC software platform
The PC collection program is implemented using VC ++ and directly calls the driver provided by Philips to read and write data, which greatly reduces the development difficulty and risks. In this design, the PC software design includes the application interface design, multi-threaded data collection, storage and processing module design, as well as the communication dynamic link library design with the USB underlying driver.
2 USB Interface Module Design
2.1 USB interface chip
The USB interface chip ISP1581 has the characteristics of small size, high speed, and relatively simple interface with single chip microcomputer. In addition to control endpoints, ISP1581 has seven input (in) endpoints and seven output (out) endpoints. The data transmission mode and the size of the data cache (FIFO) can be flexibly configured for each endpoint, and the maximum capacity of the endpoint FIFO can reach 2 kb. The ISP1581 chip requires the support of the microcontroller firmware during configuration enumeration. Once the configuration and driver loading are completed correctly, the microcontroller can perform read and write operations on the ISP1581 chip just like the ordinary memory, to send or receive data.
2.2 Firmware Programming
USB communication is initiated by the PC host. In this structure, the firmware always waits for the host command and then runs the corresponding program according to the command. The basic idea of firmware is to adopt modular design, which is divided into seven modules, such as main. C. The ISP1581 firmware structure 2 is shown. In the figure, Main. c is the main loop, ISR. C is mainly responsible for interrupt processing, and chap9.c is mainly responsible for responding to host requests. Your applications can also be included in the main. c loop in the future.

2.3 Single Chip Microcomputer Program Design
Single-chip microcomputer programs mainly include the initialization module, peripheral Flash, EEPROM, RAM, LCD display, buttons and Other Read and Write control modules, USB interface chip firmware module, a/D sampling mode, speed, and FPGA hardware control module for reading and writing sample data. The guiding ideology of this design is: to make full use of the advantages of PC and embedded systems, the requirements for MCU end should be simplified as much as possible. The specific software process 3 is shown.

USB, as a communication interface, must be configured first before sending/receiving user data. In a loop, you must check whether there are host configuration commands at any time. The configuration enumeration process is a complex part of USB firmware programming, as shown in process 4. After the USB device is connected to the host and recognized by the host, the host sends a SETUP package at the default address (00 H). The new device must receive the package and respond to the request. Then, the host sends an input packet to read the device descriptor, preliminarily determines the device attribute, then sets the device address, and then reads the various descriptors of the device to identify and configure the device. It can be seen that the Host reads a large amount of data during the device configuration process. Once the device receives a SETUP package, it determines the request type of the host, then enter the request processing loop to wait for further commands of the host. If you receive an IN token again, data is written to the control endpoint and the endpoint is written again based on the data length until the data is sent. USB standard requests include reading device descriptors, configuration descriptors, endpoint descriptors, setting addresses, and Configuring devices. Vendor requests are customized by users.

After receiving data from the host, ISP1581 sets the interrupt register mark in the chip as needed, and then applies to the microcontroller for interruption. The process of the interrupt service program is shown in step 5. After the MCU responds to the interrupt, it first reads the interrupt mark register and judges the interrupt source, and then sets the corresponding mark. In the user's sending/receiving program, the corresponding action is generated based on the corresponding flag. For example, if the host sends a piece of data to ISP1581, after receiving and handshaking the ISP1581, set the interrupt mark and request the interruption. You can read the data in ISP1581 if you find a data receipt mark in your task. When ISP1581 sends data to the host, the host sends an IN-type token to initiate a transmission. If the FIFO status of the corresponding ISP1581 endpoint is not empty at this time, the data is sent immediately, apply to the microcontroller for interruption. If there is still data to be sent after the response is interrupted, write data to the ISP1581 FIFO; otherwise, clear the interruption mark directly. The handshake between the host and the Data Collector must be designed in advance.

According to the input transmission requirements, in the specific design, in addition to the primary data transmission endpoint, a data buffer is configured with a 64-byte endpoint that works in the interrupted transmission mode as the command port, communicates with the host. If the host wants to read data from the device, it first sends a READ command. After the MCU receives the command, it writes data to the FIFO of the master data endpoint, and then the host sends a read token, data can be sent. Through the command port, you can also send various commands to control the actions of the data collector.
3 FPGA data acquisition module design
3.1 Module Division
The FPGA module is divided into A/D interface, FIFO, single-chip microcomputer interface, DMA Interface Control, master controller and other modules. Some registers that can be written by single-chip microcomputer are set. The A/D Acquisition speed can be flexibly configured, including the null, full, data writing, and read speed of the FIFO. The entire module is written in the OpenGL language. A slight modification can be performed on a variety of A/D chip interfaces. The entire design is completed in ep1c12 of the cyclone series of Altera. It can also be implemented on the acex1k series ec1k100 device with a working clock frequency of 50 MHz.
To improve the system flexibility, lattice's ispPAC80 programmable filter is used as the input filter in the signal conditioning and Filtering module, which can flexibly set the cutoff frequency of the anti-aliasing filter, the maximum cutoff frequency can reach 750 kHz, which can fully meet the filtering requirements of medium and high frequency signals. FPGA can be used as A/D controller with a variety of A/D chip interfaces. This design uses TI's 10-bit high-speed A/D chip tlc876. The chip works in pipeline mode, with a maximum sampling rate of 20 Msps.
3.2 interfaces with single-chip microcomputer and ISP1581
In the process of interface between FPGA and single-chip microcomputer signal, a synchronous design method is used. That is, the I/O signal of the single-chip microcomputer is sampled and synchronized to obtain the time when each signal is rising or falling along, and the synchronous pulse is output, then, at these time points, the system is controlled based on the appearance of the synchronous pulse. The advantage of this design is that synchronous state machines can be used in the design to achieve high running speed and stable working performance. This is also the recommended method for FPGA Digital System Design by companies such as Altera and Xilinx.
In order to improve the data exchange speed between the first-in-first-out (FIFO) and ISP1581, the FPGA and ISP1581 adopt the DMA mode for data exchange.
ISP1581 works in two ways, controlled by bus_conf, mode0, and mode1 pins:
(1) If the BUS_CONF pin is detected to be low during power-on, it works in the Split Bus Mode ). ISP1581 has 8-bit address/Data multiplexing bus and 16-bit DMA dedicated data cable. If the MODE1 pin is low, the ALE/A0 pin of the chip can be directly connected to the ALE pin of 89X51 for address/Data Bus multiplexing. If MODE1 is high, the ALE/A0 pin is connected to other 89X51 pins, and the user program pulls the ALE/A0 pin high/low for address/Data reuse, in this mode, MODE0 is not used or used for other purposes.
(2) If the BUS_CONF pin is detected to be high when powered on, it works in the general Processor Mode ). At this time, the MODE1 pin is not used (Vcc can be connected), and The MODE0 pin can be connected to low/high levels, so that the read/write pins of the chip can comply with the read/write specifications of the Motorola/89X51 microprocessor respectively. Therefore, the ISP1581 chip can work in the split bus mode to easily interface with the 8051 series single-chip microcomputer. Its AD [] can be reused as the data/address bus, RD, WE, and ALE are respectively read, write, and address locks. DATA [] is used as the dma data bus.
DMA-related pins in the ISP1581 CHIP include DREQ, DACK, DIOR, and DIOW. Before DMA transmission, you must set the working mode, initialize the DMA registers, and then write a command to the DMA command register to start the DMA transmission. Transmission modes include master, slave, IDE, and ATA. The general data acquisition system is suitable for the slave mode. In this mode, after the MCU receives the start acquisition command from the host, it immediately command FPGA to start sampling, and then Command ISP1581 to start DMA transmission, ISP1581 pulls the DREQ pin up to request data. At this time, FPGA prepares the data and lowers the DACK pin. After the data is prepared, a read pulse is generated on the DIOR line, for ISP1581 to read data into the internal FIFO. The DMA can also use the master mode. In this case, the read pulse DIOR is generated by ISP1581. Figure 6 shows the DMA working sequence.

4 pc multi-thread data collection program design
USB data transmission uses the virtual pipe concept, which allows 127 devices to be connected at the same time. Each device can have multiple endpoints, and each endpoint can form a connection with the host to form the smallest entity for communication. During data transmission, as long as the bandwidth permits, the host can communicate with several endpoints at the same time. Therefore, you must enable multiple threads in the Host application program for communication. In this design, the command endpoint and data endpoint are separated. The command endpoint is configured as an interrupt or batch transmission mode. In the Host application, enable a thread to communicate with this endpoint, and enable another thread to transmit sample data, the two transmissions do not affect each other. The user interface uses another thread, so that the application can respond to user commands at any time during transmission. In the specific design, click the data collection start command to create and start a collection thread. A flag variable is set in this infinite loop thread function. If the variable is true, the thread function continues to run; otherwise, the thread stops collecting data. In this way, the user interface thread can control the thread running by modifying the thread running flag variable. One problem with multi-threaded collection programs is that a thread function must be a global function and does not belong to any class. In this way, it cannot be a private or protected member of the handler class, to solve this problem, the thread function allows a pointer parameter to be transmitted during creation. Therefore, a structured data type can be constructed, and a data member contains a pointer to the class. When a thread is created, the pointer of the class to be accessed is included in a structure variable defined in the preceding statement, and the pointer of this structure is passed as a parameter to the thread function. In this way, a class object can be defined in the thread function, and the aforementioned class pointer can be assigned to it to access all the members of the object through the class pointer. The system works very stably after multi-threaded programming is used in this design.
Currently, data collection systems at home and abroad commonly use a variety of interface methods, such as RS232 serial port, parallel port, ISA bus, PCI bus and so on. Although these bus interfaces have their own advantages, they all have their insurmountable shortcomings and are gradually eliminated. The USB interface has special advantages such as convenient connection, no external power supply, plug-and-play, hot swapping, and dynamic driver loading, simple, fast, and reliable connection and communication can be achieved between the host and the data collection system. In this design, the ISP1581USB interface chip and FPGA technology are used to build a flexible universal data acquisition system. The system makes full use of PC's large storage capacity, powerful data processing capabilities, high-definition Big Screen Display (compared with embedded systems), as well as the real-time and flexibility of embedded systems. Currently, this platform is being used to build a collection and analysis system for mechanical vibration and noise in the acoustic chamber environment. This system will certainly have a wide range of application prospects in many fields such as intelligent instruments and industrial automation.
References
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