Design of Video Image Acquisition and Processing System Using FPGA and USB Bus

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Source: Beijing University of Science and Technology Author: Zhou jianbo Yan Xianfeng Wang changsong sun Honglin

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SummaryA High-Speed Image Acquisition and Processing System with FPGA as the core chip is built. The image acquisition frequency can reach 13.5 MHz, the video A/D chip SAA7111A is used to convert the TV signal into A digital signal, and FPGA is used as the Controller to save the digital signal into the SRAM for processing and extract useful data; the system also uses the ezusb2stmq chip for data processing and PC transmission.

KeywordsVideo Image; signal processing; FPGA; VHDL; EZUSB; video A/D

Traditional image acquisition cards based on ISA, PCI, and other bus have been widely used. However, they are slow in speed and have simple processing functions. For special requirements, they often need to be processed later, in this paper, A high-speed image acquisition system is built, which consists of FPGA (field programmable gate array), video A/D chip SAA7111A and USB bus. the system can be programmable on site as needed, and has the advantages of good versatility and low cost. in FPGA, Hardware Description Language (VHDL) is used to implement FPGA, which can replace single-chip microcomputer and DSP in the data collection system to control the data collection process.

PHILIP's video A/D chip SAA7111A has four-channel video input, and both anti-mixed filtering and Comb Filtering are integrated into the chip, bringing great convenience, however, the integration of the internal PLL technology greatly reduces the reliability and design complexity.

CYPRESS's ezusb2108qc chip is developed for the USB 1.1 protocol. It is compatible with full-speed and low-speed transmission and features are highly integrated. the chip integrates an enhanced 8051 processor, an "intelligent" Serial Interface Engine (SIE), a USB transceiver, an I2C bus controller, on-chip RAM and FIFO.

1. Image Acquisition and Processing System Design

The system consists of video A/D chip, FPGA control module, data storage module SRAM, EZUSB interface module, and PC application program. FPGA Program is written in VHDL, as shown in figure 1.

2. A/D conversion of Video Signals

 SAA7111A provides four analog input channels, which can be programmed to use one or more of the Channel Video signal input chips, all the way through the buffer output from the AOUT pin, this signal is used as a video monitoring signal to detect whether there is video signal input. The other signal is converted by mode/number to generate a digital color signal and Brightness Signal, brightness Signal Processing and color signal processing respectively. the result of Brightness Signal Processing is sent all the way to the color signal processor for Comprehensive processing to generate gray-level signals Y and UV. After formatting, It is output from the data line VPO, among them, the 8-bit high is Y, and the 8-bit low is UV. The other way enters the synchronization separator, And the PLL generates the corresponding line synchronous signal HS and field synchronous signal, at the same time, the digital PLL drives the clock generator module to generate the LLC and 13.5MHz LLC2 clock signals at the 27MHz video signal. for normal operation of SAA7111A, 32 internal registers must be correctly configured. The EZUSB an21_q is written to the internal register of SAA7lllA through the I2C bus.

3. FPGA Control Module

After analyzing and dividing the system functions, you can divide the design into several sub-modules. each sub-module associates with each other through the internal handshake signal and completes relatively independent functions. finally, combine the sub-modules to obtain the system-level functional chip. divide FPGA into the following functional sub-modules: the input signal buffer module, the jitter elimination module, the SAA7111A interface module, the SRAM interface module, the real-time insertion end mark module, the buffer module defaults 0, the multi-channel selector DATA-MUX, and the DATA processing module DATA_Proc, 2. The modules are communicated through intermediate signals to achieve data transmission and control.

SAA-INTERFACE module 3.1

 The main function of the SAA_INTERFACE module is to receive data signals and status signals from SAA7111A and implement interfaces between FPGA and video A/D chip SAA7111A, based on these signals, the storage address of the corresponding pixel gray information is generated. under the control of the clock signal LLC2, the data storage and writing addresses and reading addresses in the SRAM are completed, and the indication signals for ping-pong operations on the two SRAM instances are generated.

By analyzing the sequence diagram of the State signal output by SAA7111A, the following conclusions can be obtained:

(1) Each line of images has a total of 864 pixels, 0 ~ 719 is a valid pixel, 720 ~ 863 indicates the horizontal invisibility phase, and the pixels in the invisibility period are invalid pixels.

(2) The starting condition for each line of image is: when the field reference signal VREF is logical '1', HREF generates a rising edge. the condition for the end of each line of image is that the HREF signal is in the field invisibility stage when VREF is in the logical '0' state.

(3) When RTS0 is the logical 'l', VREF generates a rising edge. the condition for the end of each frame is that, when RTS0 is the logical 'O', VREF generates a descent edge.

Because the CVBS of the composite video signal is obtained by means of line-by-line scanning, while the computer monitor displays the image by line scanning, the data written into the SRAM must be written in line-by-line, the data read from SRAM must be read row by row. when reading the SRAM, since the parity field has been "interfaced" into the SRAM, you only need to read the data row by row.

3.2 SRAM_INTERFACE Module

 The main function of the interface module SRAM_INTERFACE is to interface the interface with the SRAM memory. because two pieces of SRAM are used, there should also be two SRAM interface modules in FPGA. This module makes a judgment based on the current status, so as to send the corresponding control signal and address signal to the SRAM, write and read data.

3.3 INSERT_FLAGS Module

In order to display the acquired image on the host computer, in addition to the corresponding pixel information, it is also necessary to provide the line synchronous signal and the field synchronous signal. The system does not provide the special line synchronous signal or frame synchronous signal, instead, the row and frame synchronization signals of the video stream are replaced by inserting the mark data at the appropriate time.

The INSERT_FLAGS module inserts the custom end ID of the row into the data stream at the end of the row. At the end of the frame, it inserts the end ID of the frame into the video stream, this makes it easy for the host computer to reproduce and process the image information.

3.4 DATA_MUX Module

 The DATA_MUX module controls the flow of data and processes data. it receives the original data VPO from SAA71llA, the real-time inserted rows, the frame end identification signal VP () _ FLAGS, and generates the final continuous data stream VPO_ALL with the field and frame end identification, and control the flow direction of VPO_ALL. when WRlRD2 is the logic '1', VPO_ALL is written to SRAMl and the data already stored in SRAM2 is read to the DATA_Proc module. When WRlRD2 is the logic '0, data of VPO_ALL is written to SRAM2, and the data of SRAM1 is read to the DATA_Proc module.

3.5 DATA_Proc Data Processing Module

The DATA_Proc module is used to process the collected data. According to the project requirements, the module filters the signals and extracts edge information to extract valid data and reduce the amount of data transmitted. to reduce the workload, Xilinx SystemGenerator software was used to design this module.

Ceneratcor is an FPGA-assisted design tool developed by Xilinx and Mathworks. You only need to build the model in simulink. Start SystemGenerator to automatically generate the VHDL source program and other engineering files, the system model is mapped to the FPGA of the target device for hardware implementation.

3.6 FIFO module

The clock that the video signal enters FPGA is 13.5 MHz, while that of the USB interface chip is 12 MHz. this leads to the asynchronous timing design problem. because data transmission across clock domains is required, buffer data units must be added between FPGA and EZ_USB. this buffer is generally implemented by asynchronous First-In-First-Out (FIFO. asynchronous FIFO writes data to every write clock, and reads data from every read clock. These two clocks are asynchronous.

The working principle of FIFO is: when the write clock is on the rising edge, when the write is valid, the data written on the Data Bus is written to the storage unit corresponding to the write address in the dual-port RAM; the data in the two-port RAM corresponding to the read address is always output to the read data bus, and the data is output when the read address is valid.

4 ezusb Module

In the system, ezusb1_1 mainly completes two aspects: the configuration of SAA7111A and the data transmission based on the Fast Synchronous transmission mode.

In order for the video decoding chip saa7111a to work properly, the internal registers must be correctly configured through the I2C bus. When saa7111a is configured through I2C, the data written format is: first, the start signal, then there is a 7-bit slave address and a direction bit ('0' indicates writing data to the saa7111a register, and 'l' indicates reading the corresponding register) with a total of 8 digits of data, at this time, the slave should send a response signal to the host. the address of the register written to the slave machine and the response signal of the slave machine are followed by the data to be written into the sub-Address Register and the end signal.

The USB Bus supports four data transmission modes: control transmission, interrupt transmission, and other time transmission and block transmission. ezusb 2131q supports fast and other time transmission methods. To speed up data transmission, this method is used for data transmission, enable the FIFO module in FPGA to communicate directly with the Data Bus in ezusb.

To transmit data in fast synchronization mode, you need to configure 2131 as follows:

(1) It can interrupt SOF and enable nuclear energy within 51 to receive sof interruptions, so as to ensure 1 ms of data transmission.

(2) When the system uses the wait time to transmit the In8 endpoint, you must set inisoval to "00000001 ".

(3) set the size of the FIFO when the In8 endpoint will be used. In order to speed up data transmission, set the size of the FIFO to 1024.

(4) set the register portacfg and set the 4th-bit and 5th-bit multiplexing functions of the Pa Port. The multiplexing function is the FRD and fwr signals transmitted at the same time.

(5) set the register fastxfr to enable fast time transmission mode, set the nfrd low level to be valid, and set the width and phase of the nfrd.

To respond to SOF interruptions, you need to write a data processing program in the interrupt response function ISR_Sof () to transmit data to the IN8DATA internal register. On the other hand, you need to clear SOF interrupt requests and USB interrupt requests, so that the program can make the correct response to the next SOF.

5 PC applications

 EZUSB universal driver GPD (general purposedriver) is a universal device driver used with EZUSB peripheral interfaces, which provides a way for applications to access EZUSB hardware. the EZUSB Development Kit provides the Default Driver file: EZUSB. SYS. for applications, call CreateFile () to open the device and obtain the handle to access the device driver. the user program uses the DeviceIoControl () function to submit the control code, and sets the I/O buffer for the device handle returned by the CreateFile () function.

Connect to the EZUSB device of the host, and GPD creates a connector for it. A link character. the CreateFile () function is called to obtain the device handle generated by the driver. the EZIU3SHW Development Kit provides I/O control codes. These I/O control codes can be used to implement USB communication conveniently. When using the fast transmission mode, you need to set IOCTL_EZUSB_START_ISO_STREAM, IOCTL_EZUSB_READ_ISO_BUFFER, IOCTL_EZUSB_STOP_ISO_STREAM and other control codes are provided to the function DcviceIoControl () to enable the functions such as transmission at the same time, reading at the same time, transmission at the same time, and transmission at the same time.

6 conclusion

The system uses FPGA as the collection and processing part, which can increase the processing speed of the system and greatly enhance the flexibility and adaptability of the system. The specific performance is as follows:

(1) the system performance is greatly improved. Because dual-SRAM is used as the data exchange zone, FPGA uses ping-pong technology to transmit data, which improves the transmission speed.

(2) Strong system adaptability and flexibility because FPGA programmable logic devices are used to collect and process data, as long as FPGA logic is slightly modified for different video image signals, this allows you to collect signals.

(3) The design structure is simple and debugging is convenient. The FPGA peripheral hardware circuit is simple. In the hardware design, the complexity of the hardware design can be greatly reduced.

The combination of FPGA and USB technology greatly improves data processing capabilities and is conducive to system upgrades. this design is used to transmit the amount of data processed at present, and the ezusb1_1 chip can be used. if you need to transmit a larger data volume, you can use CPYRESS's USB chip cy7c68013 instead. this instance can also be used in real-time data collection, audio and compressed video data transmission and other fields.