Design of RS-485 interface circuit

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The RS-485 interface is a serial bus based on balanced transmission and differential reception. It has strong anti-common mode interference capability and has a long transmission distance at an appropriate baud rate. At the same time, it is easy to expand the network, it is widely used in many industrial sites.

In the energy-saving Lamp Life testing environment, it mainly interferes with the strong electrical interference from the switch and life testing, the electromagnetic interference from the switch, and the interference from air circulation equipment. At the same time, due to the high temperature in the life testing environment, the high-power system is complex and puts forward higher requirements for system operation. The Life Check System must report the running status, ambient temperature, voltage, and other parameters of each energy-saving Lamp in real time, and calculate such parameters as the life-saving Lamp Life and lighting. It can be seen that the system has a large amount of data transmission and strong real-time performance. Therefore, the topology structure and communication protocol of the physical bus are particularly critical.

2 Interface Design
Good interface design should ensure good anti-interference, stability and scalability of the system on the hardware. This system selects a half-duplex interface chip sn65hvd3082 with high cost performance. It has the following features:
① Meet or exceed the requirements of TIA/EIA-485A standards;
② Low static current consumption-the effective mode is less than 0.3 mA, And the off mode is l na;
③ The output signal of the optimized drive ensures low Emi At a transmission rate of kbps;
④ 1/8 unit load-up to 256 nodes on one bus;
⑤ Bus pin ESD protection exceeds 16 kV;
⑥ Coverage of industrial standard sn75176;
7. Failure Protection.
Based on sn65hvd3082 RS-485 interface circuit, there are usually three solutions.

(1) RS-485 interface circuit of direct control Transceiver
This method uses the Controller to switch the sending and receiving enable to control the sending and receiving of interface circuit data. Because direct sending and receiving are adopted, the conversion between sending and receiving is required. Only an additional controller can be added to control the conversion between sending and receiving. At the same time, the controller must be used to store and forward all transmitted data, in this way, each frame of data is transmitted, at least one unit of reception time is lost (the time for storing and forwarding 1 frame of data ). This scheme is not conducive to real-time communication with a large amount of data, and in the transmission and receipt switching process, in the VA and VB (VA and VB are the voltage of A and B of RS 485 bus respectively) generation of step voltage. This step voltage interferes with the receiver's reception.

(2) The RS-485 interface circuit of automatic transmission and receiving Conversion
The dotted box shown in Figure L is an interface circuit. By analyzing the truth table, the sending and receiving processes are as follows:
When the sending side di = O, de/Re = 1 sends the O level, the receiving end RO = O; when the sending side di = 1, de/Re = 0, va = VB = 2.5 V, and the receiving end is RO = 1 due to the pull-up resistance.

The txo end of this interface circuit is tested by adding a 1 kHz TTL square wave. When the 120 Ω end resistance is not added, both the 485-a and 485-b ports of the interface chip have a voltage variation process of about 50 μs, as shown in figure 2. The rising edge of the RO waveform at the receiving end has a significant delay of about 30 ~ 40 μs (compared with the DI of the data sending end), resulting in a large transmission error. When the 120 Ω resistance is added, the delay is significantly reduced, about 3 μs.

During High-power transmission, the transmitter is in the high-impedance state, and all interfaces on the bus are in the receiving state. The bus is idle and allows other interfaces to send data, so it is easy to introduce bus conflicts. In particular, when the level ratio of the continuous transmitter is higher, the longer the transmitter is in the high-impedance state, the more likely the introduced bus conflict will be.

(3) Zero Delay RS-485 Interface Circuit
Zero Delay RS-4185 interface circuit is mainly used 74hcl4 and the resistance, capacitance and other components in the circuit to form a very short delay circuit, its main role is:
① When the transmitter sends a high level, the transmitter is no longer in the high-impedance state in the short delay, and the drive current still exists. In this way, the anti-interference capability of the interface can be increased to a certain extent.
② We can see from the truth table. for the receiver, when vid = VA-VR is greater than or equal to a O.01 V, RO = 1; At the sender end, when de/Re = 0, the VA and VB of the sender drive are both high impedance states, in this case, VA = VB = 2.5 V. Therefore, for the receiver RO = 1, and for a short delay, the number of DI = 1 and De/Re = 1. so RO = 1. it can be seen that in the short delay and De/Re = 0 time, the receiver RO = L, This completes the transmission and receiving of the high level, and there is no delay in the rising edge of the receiver, zero latency, as shown in 3.

Replace the RS-485 interface circuit of the automatic receiving and receiving conversion in Figure L with the RS-485 interface circuit of zero delay, 4 shows. Similarly, a 1 kHz square wave is added to tx0 to test the circuit. The result is that there is no delay in the rising edge of the receiver Ro. This has nothing to do with whether to access the end resistance of 120 Ω, and confirms the above analysis.

In Figure 2 and 3, the voltage at which the dotted arrow points is 2.5 V.

In Figure 4, The R3 and C0 parameters are selected based on the system's transmission speed to achieve zero latency. The higher the transmission speed, the lower the latency. Select R3 = 22 KB, C0 = 1000 PF.

The RS-4t85 interface circuit and the zero-delay RS-485 interface circuit have deficiencies, that is, in the sending end to send continuous high-frequency, logically the sending end is in the sending status, the receiving end is in the receiving status. But in fact, the De/RE of all sn75hvl53082 interfaces is 0. Therefore, all the sending and receiving ends are in the receiving status. This cannot be ignored in the peer-to-peer network structure, because during this period, the bus is idle and allows nodes to send data.

The master-slave network structure is used here, so this problem will not affect the system work.

3. Network Topology
The design of the network topology is based on the actual needs of the life detection system. The design goal is to meet the detection requirements of Lo's life frames and each life frame has 64 nodes, it is easy to expand in hardware and software, and the cabling is reasonable. Therefore, the master-slave network structure and the physical structure adopt a star topology, as shown in Figure 5. The topology consists of two levels of bus and consists of the following devices:
RS-232 to RS-485. Realize RS-232 to RS-485 electrical signal conversion, which is the first level RS-485 bus.
② 485 hijb (hub) with 10 ports ). As shown in 6, 485hub is composed of one host and ten slave RS-485 interfaces with zero latency, which is the basis for implementing the master-slave structure logically. When data is sent downstream on the host, all interfaces connected to 10 slave interfaces can receive data. When a node attached to a slave interface sends data upstream, only the host node (PS) and other nodes attached to the same slave interface can receive data. This is the second level RS-485 bus.
③ Single-chip microcomputer node. There are four types of nodes: energy-saving Lamp status collection node, temperature collection node, power supply voltage collection node, and mode control node. The communication interface of each single-chip microcomputer node uses the zero-delay RS-485 interface circuit, each node has its own address, used for PC terminal addressing.

Theoretically, a sn75hvd3082 bus can connect up to 256 nodes, so more nodes can be expanded on each slave interface; at the same time, the RS-232 to RS-485 converter bus can also be connected to more 485hub. In this way, the hardware can be expanded.

4. Communication Protocol
It adopts a baud rate of 9600 bps, a fixed frame length structure, and a frame length of 10 bytes. Frame information is defined as follows: frame header (0x55 0xaa), command (1 byte), data (4 byte), slave address (2 byte), verification (1 byte ).

Frame verification and frame timeout are adopted in communication protocols to achieve the purpose of anti-interference.
① Frame verification: Accumulate and verify. During sending, the frame header, command, data, and slave address are added and the lowest byte is used to fill the verification domain. If the node is not in the receiving status, start sending; otherwise wait; if the node is not in the receiving status and receives 10 bytes completely, add the frame header, command, data, and slave address fields and compare them with the verification domain. The same result indicates that one frame of data is successfully received.
② Frame Time-out: The Frame Time-out is defined as that, when the first byte is received, the receiving status is displayed, and 8 ms timing is set. After each byte is received, 8 ms timing is reset. Normally, it takes about 1 ms to receive a byte. If it exceeds 8 ms, the system will exit the receiving status, discard the current received frame, return to the idle status, and wait for the next frame to receive.

In programming, the definition of frame timeout is related to the program architecture and the baud rate. In principle, it is only necessary to receive time greater than 1 byte. 8 ms depends on the program architecture.

5 test conclusions and application prospects
After the addresses of all nodes are set, the system can be tested on site. The test solution is to run the test software on the PC, and send the test command to round-robin all nodes every 50 ms. Each sending request requires that data be returned. Otherwise, the request is considered as a communication error. If the software runs for seven consecutive days and no errors are found, the system is stable and reliable.

At present, the designed life-saving energy-saving Lamp detection system has been put into use at the site, and the operation effect is good. This system design concept serves as a reference for designing a real-time intelligent detection system with a large number of nodes and a large amount of data. It will be widely used in the field of automatic detection.