Design of Power gating (Overview)

Leakage power consumes more power as the CMOS circuit process progresses.

Power domain switches are typically controlled by the timer in the hardware and the power management software at the system level, and need to be trade-off in a few ways:

1) possible savings of leakage power,

2) power and time consumption of entry and exit,

3) Power sleep and active frequency,

Power gating can completely turn off dynamic power consumption, but leakage will only be reduced and will not disappear because power gating technology still needs to add some isolate cells

and retention cell, bringing leakage.

The effects of power gate on different sub-system:

For the cache CPU System,power gating can greatly reduce the leakage and eliminate dynamic Power, but the restoration of the cache content will take

A lot of time and energy;

For peripheral System,device driver may need special initial hardware sequence, which makes the burden of software heavier;

For multi-processor CPUs, each time a core completes its own task, it can power gating to clear its cache, but Big-little's core call

Some algorithm support is required.

External power gating, which requires multiple voltage regulator in the board level, brings the corresponding RC, increases the board level burden, and the switch time spends too much.

So now use Internel power gating more.

A typical power gate system:

Because the power gated block output due to the presence of capacitance, voltage loss is relatively slow, so that the voltage in the vicinity of the VT for a long time, may appear fox current (crowbar)

Therefore, it is necessary to join the isolate unit, and support two voltage operation to improve timing closure.

In order to be able to revert to the original state, you also need to add rentention register to replace the regular register. Retention register will attach a shadow latch in

After regular register, the high VT unit is used to reduce leakage, but timing will not be very good.

Structure of power switch: Fine grain power gating and coarse grain power gating.

Fine grain Power gating says that each switch is placed inside the cell. This makes the area increase 1x-3x.

The advantage of this is that you can better control the timing problem caused by ir-drop.

Coarse grain Power gating, a block gates has a set of switch cells. More economical area.

However, such a design must control the inrush current of the power supply and control the Ir-drop in the power network.

Currently the most used.

Key points in the Power gating design:
1) design of Power switch;

2) Design of Power gating Controller;

3) selection and insertion of retention register and isolation cell;

4) Influence of Power gating on area and timing;

5) clock and reset module design;

6) Verfication of Power State transaction;

7) DFT design strategy for manufacturing;

Design of Power gating (Overview)