Detailed explanation of CP operation commands in arm MCR/MRC

1. MCR: transmits the value of normal register in arm to CP register.

Format: MCR cpx, OP1, src_reg, dst_reg1, dst_reg2, OP2/* op, operation code; SRC, source; DST, destination */

Cpx: integer in the range 0 ~ 15 defining coprocessor.

OP1: integer in the range 0 ~ 7 selecting different coprocessor Functions

Src_reg: integer in the range 0 ~ 15 defining GP register in the processor core ining the value to read or write

Dst_reg1: integer in the range 0 ~ 15 defining the target coprocessor register.

Dst_reg1: integer in the range 0 ~ 15 selecting guest SS banks of 16 coprocessor registers

OP2: integer in the range 0 ~ 7 selecting different coprocessor functions.

 

E.g. MCR P15, 0, R0, C7, C7, 0/* flush V3/v4 cache */

Explain: this operation transfers the value in R0 to the C7 of CP15

2. MRC: transmits the value of CP register in arm to normal register.

Format: MRC cpx, OP1, dst_reg, src_reg1, src_reg2, OP2

E.g. MRC P15, 0, R0, C1, C0, 0

Explain: this operation saves C1 and C0 values in P15 to R0.