Detailed explanation of the S3C2440 clock

S3C2440 clock

C code about clock in ads1.2:
Changempllvalue (mpll_val> 12) & 0xff, (mpll_val> 4) & 0x3f, mpll_val & 3 );

Changeclockdivider (Key, 12 );

 

1) Relationship between flck, hclk and pclk
The S3C2440 has three clock types: flck, hclk, and pclk. According to the S3C2440 official manual: fclk is used by ARM920T,
Hclk is used for AHB Bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB Host block. that is, the bus clock, including the USB clock.
Pclk is used for APB bus, which is used by the peripherals such as wdt, IIS, I2C, PWM timer, MMC interface, ADC, UART, gpio, RTC and SPI. i/O interface clock. For example, the serial port clock is set from pclk;
So what is the relationship between these three clocks?

These three clocks are usually set to a, relationship, that is, if the clock speed flck is 400 MHz, then according to the settings, then hlck is 100 MHz, Plck is 50 MHz. The clkdivn Register indicates and sets the relationship between the three clocks. If clkdivn is set to 0x5, the ratio is, provided that camdivn [9] is 0.

2) Relationship between input clock fin and clock speed fclk
The modern CPU basically uses much lower clock input than the clock speed, and uses the phase-locked loop in the CPU for frequency doubling. For S3C2440, there are two common input clock Fin: 12 MHz and 16.9344 MHz. How does the CPU multiply the fin to fclk?
S3C2440 uses the mdiv, pdiv, and sdiv multiplier to set fin to mpll, that is, fclk. Mpll = (2 * m * fin)/(p * 2 ^ s) where M = (mdiv + 8), P = (pdiv + 2), S = sdiv.
The register mpllcon is used to set the multiplier. In theory, you can set this register to implement different frequencies. However, it is not easy to set an appropriate frequency due to various constraints, the Manual lists some frequently used frequency tables, for example, assuming that the input clock fin = 16.9344 M, mdiv = 110, pdiv = 3, sdiv = 1, using the above formula, fclk = 2*16.9344*(110 + 8)/(2 + 3) * 2) = 399.65.

3) about USB clock
S3C2440 has two Phase-Locked Loops. One primary phase-locked loop mpll is provided to fclk, And the other upll is provided to the USB clock (48 MHz), just like mpll, upll is also generated by setting the frequency division factor in the upllcon register. The formula is slightly different: upll = (M * fin)/(p * 2 ^ s) where m = (mdiv + 8), P = (pdiv + 2), S = sdiv. Similarly, you can obtain a proper value through the Table query.
Finally, it is worth mentioning that the third-bit divn_upll in clkdivn is used to set the relationship between the USB clock uclk and upll. If the upll is 48 MHz, it should be set to 0, it indicates a relationship. Otherwise, it is a relationship. USB clock where the crystal oscillator gets upll by setting upllcon for frequency doubling, and then upll gets the uclk to provide the USB clock by setting the third divn_upll of clkdivn. the USB clock frequency must be 48 MHz, therefore, when setting the upllcon and clkdivn registers, set the uclk result to 48 MHz. Generally, set the upll value to 48 MHz or 96 MHz, therefore, when the clkdivn register is set, it is obtained at 48 MHz by no or 2.