Detailed meaning of JTAG

 

Detailed meaning of JTAG!

JTAGIt is short for the header Letter "Joint Test Action Group (Joint Test behavior Organization)", which was founded in 1985, it is a PCB and IC testing standard developed by several major electronic manufacturers. JTAG was recommended to be approved by IEEE as IEEE1149.1-1990 Test Access Port and boundary scan structure standard in 1990. This Standard specifies the hardware and software required for border scanning. Since 1990
After the annual approval, IEEE supplemented the standard in April 1993 and April 1995 to form the currently used IEEE1149.1a-1993 and IEEE1149.1b-1994. JTAG is mainly used in the following scenarios: Circuit boundary scan testing and System Programming of programmable chips.

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International Standard test protocol
JTAGIt is also an international standard test protocol (IEEE 1149.1 compatible) and is mainly used for internal chip testing. Most advanced devices now support the JTAG protocol, such as DSP and FPGA Devices. The standard JTAG interfaces are four lines: TMS, TCK, TDI, and TDO, which are the mode selection, clock, data input, and data output lines respectively. The related JTAG pins are defined as: TCK is the test clock input, TDI is the test data input, data is input through the TDI pin JTAG interface, and TDO is the test data output, data is output from the JTAG interface through the TDO pin. TMS is selected for the test mode. TMS is used to set the JTAG interface to be in a specific test mode. TRST is the test reset, and the input pin is effective at a low level. GND

TI also defines an interface called SBW-JTAG, which is used to implement the JTAG interface on a chip with fewer pins through the use of at least pins. It has only two wires, SBWTCK and SBWTDIO. In actual use, it is generally connected through four lines, such as VCC, SBWTCK, SBTDIO, And GND, so that the connection can be conveniently realized without occupying a large number of pins.

JTAG was initially used to Test the chip. The basic principle is to define a Test Access Port (Test Access Port) inside the device to Test the internal nodes through a dedicated JTAG Test tool. JTAG testing allows multiple devices to be connected together through the JTAG interface to form a JTAG chain, which can be used to test each device separately. Currently, the JTAG interface is often used to implement ISP (In-System Programmable; online programming) and program FLASH and other devices.

The JTAG programming method is online programming. In the traditional production process, the chip is pre-programmed and then installed on the board. Therefore, the simplified process is fixed to the board and then programmed with JTAG, this greatly accelerates the project progress. The JTAG interface can be used to program all components in the PSD Chip.

In terms of hardware structure, the JTAG interface consists of two parts: the JTAG port and the Controller. Devices compatible with the JTAG interface can be microprocessor (MPU), microcontroller (MCU), PLD, CPL, FPGA, ASIC, or other chips that comply with ieee1149.1 specifications. The ieee1149.1 Standard specifies that each pin corresponding to the digital IC chip has a shift storage unit, called the boundary scanning unit (BSC. It associates the JTAG circuit with the kernel logic circuit and isolates the kernel logic circuit and chip pins. The Boundary Scan register BSR is composed of all the Boundary Scan units of the integrated circuit. The Boundary Scan register circuit is only performing JTAG
Valid during testing and ineffective when the integrated circuit works normally without affecting the functions of the integrated circuit.
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Border scan technology
JTAG is a so-called border scanning technology.

Edge scanning testing was developed in the middle of 1980s as a JTAG interface to solve the problem of physical access to the PCB. This problem was caused by the increasingly crowded assembly of the Board due to the new packaging technology. The Boundary Scan embeds a test circuit at the chip level to form a comprehensive circuit board-level test protocol. Using Boundary Scan-industry standard IEEE 1990 since 1149.1-you can even test, debug, Program on system devices, and diagnose hardware problems in the most complex assembly.

　　Border scan priority:

By providing Io access to the scanning chain, you can eliminate or greatly reduce the need for physical test points on the board, which significantly saves costs, because the circuit board layout is simpler, the test fixture is cheaper, the test system in the circuit takes less time, the use of standard interfaces increases, and the time to market is faster. In addition to circuit board testing, boundary scan allows programming almost all types of CPLD and flash memory on the Board after a PCB patch, regardless of the size or encapsulation type. In system programming, you can save costs and increase production by reducing device processing, simplifying inventory management, and integrating programming steps on the circuit board production line.

　　Boundary Scan principle:

　　The IEEE 1149.1 Standard specifies a four-line serial interface (the fifth line is optional), called a Test Access Port (TAP), used to access complex integrated circuits (IC ), such as microprocessor, DSP, ASIC, and CPLD. In addition to the TAP, the Hybrid IC also contains the shift register and the state machine to perform the Boundary Scan function. Data entered into the chip on the TDI (test data input) lead is stored in the instruction register or in a data register. Serial Data leaves the chip from the TDO (test data output) lead. The Boundary Scan logic timing signals on the TCK (test clock) and the TMS (Test Mode Selection) signal drives the status of the TAP controller. Trst (test reset) is optional. On the PCB, you can connect multiple ICs that are compatible with the scanning function to form one or more scanning chains. Each chain is associated with its own tap. Each scan chain provides electrical access, from the serial tap interface to each lead on each IC as part of the chain. During normal operation, the IC executes its predefined function, as if the Boundary Scan Circuit does not exist. However, when device scan logic is activated for testing or system programming, data can be transmitted to the IC and read from the IC using a serial interface. In this way, the data can be used to activate the device core, send the signal from the device lead to the PCB, read the PCB input lead and read the device output.

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Simple JTAG Cable
About simple JTAG Cables

At present, there are various simple JTAG cables, which are actually just a level conversion circuit and also play a protective role. JTAG logic is implemented by software running on the PC. Therefore, theoretically, any simple JTAG cable can support various applications, such as debug. You can use the same JTAG cable to write Xilinx CPLD and axd/adw debugging programs. The key is software support. Most software does not provide the setting function, so it can only support some type of JTAG cable.

　　Speed of simple JTAG Cable

JTAG is a serial interface. It uses the simple JTAG cable of the print port and uses the output lock of the print port to generate the JTAG sequence through I/O. It is determined by the JTAG Standard that it requires a series of operations to write/read a byte through JTAG. According to my analysis, a simple JTAG cable is used to output a byte to the target board through the print port through JTAG, on average, 43 print ports I/O are required. On my machine (P4 1.7 GB), about 660 k I/O operations can be performed per second, so the download speed is about K/43, approximately 15 K Bytes/s. for other machines, the I/O speed is roughly the same, generally between 600 KB and kb ~ 800 K.

　　How to increase the JTAG download speed.

Obviously, using a simple JTAG cable cannot increase the speed. There are two ways to increase the speed,

1. The JTAG interface is provided by the embedded system. The embedded system and the microcomputer are connected through USB/Ethernet, which requires MCU.

2. The JTAG interface is provided using CPLD/FPGA, and the EPP interface is used between CPLD/FPGA and the microcomputer (generally, the microcomputer print port supports the EPP mode). The EPP interface completes data transmission between the microcomputer and the CPLD/FPGA, CPLD/FPGA completes the JTAG timing.

Both methods have been implemented. The first method can achieve a relatively high speed. The actual measurement exceeds 200 KByte/S (Note: it is a Byte, not a Bit). However, the hardware is relatively complicated and the manufacturing is relatively complicated. In contrast, the download speed is slower, reaching 96 KByte/S as quickly as possible, but the circuit is simple, easy to manufacture, and the speed can meet the needs. The second solution also has a disadvantage. Because the CPU is not released during I/O operations, the microcomputer CPU is very busy when downloading the program.

In general, I believe that the second method is preferred for individual enthusiasts.
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Explanation of the JTAG interface
Explanation of the JTAG interface

Generally, JTAG is divided into two categories: one is used to test the electrical characteristics of the chip, and the other is used to test whether there is a problem with the chip; the other is used to Debug; the CPU that supports JTAG generally includes the two modules.

A cpu with the JTAG Debug interface module can access the internal registers of the CPU and the devices mounted on the CPU bus, such as FLASH, RAM, as long as the clock is normal, SOC (such as 4510B, 44 Box, AT91M series) built-in module registers, such as UART, Timers, GPIO registers.

The above only describes the capabilities of the JTAG interface. To use these functions, software cooperation is also required. The specific implementation functions are determined by the specific software.

For example, download a program to RAM. All SOC users know that to use external RAM, you need to refer to the SOC DataSheet register instructions to set the RAM base address, bus width, access speed, and so on. Some SOC still needs Remap to work normally. When Firmware is run, these settings are completed by the Firmware initialization program. However, if the JTAG interface is used, the relevant registers may still be in the power-on value or even an error value, and RAM cannot work properly, so the download must fail. To work properly, you must first set up RAM. In the ADW, you can Set it by using the Let command in the Console window, And in the AXD, you can Set it by using the Set command in the Console window.

Below is a command sequence for setting AT91M40800, shutting down the interrupt, setting the CS0-CS3, and performing Remap, suitable for AXD (ADS with Debug)

Setmem 0xfffff124, 0 xFFFFFFFF, 32 --- disable all interrupts

Setmem 0xffe00000, 0x0100253d, 32 --- set CS0

Setmem 0xffe00004, 0x02002021,32 --- set CS1

Setmem 0xffe00008, 0x0300253d, 32 --- set CS2

Setmem 0xffe0000C, 0x0400253d, 32 --- set CS3

Setmem 0xffe00020, 1, 32 --- Remap

If you want to use it in ADW (DEBUG with SDT), change it:

Let 0xfffff124 = 0 xFFFFFFFF --- disable all interrupts

Let 0xffe00000 = 0x0100253d --- set CS0

Let 0xffe00004 = 0x02002021 --- set CS1

Let 0xffe00008 = 0x0300253d --- set CS2

Let 0xffe0000c = 0x0400253d --- set CS3

Let 0xffe00020 = 1 --- remap

For ease of use, you can save the preceding command as a config. ini file, and enter ob config. ini in the console window to execute it.

Using other debug commands is similar, except that the command format and command format are different.

When setting ram, the set register and register value must be consistent with the setting of the program to run. Generally, the target file generated by compilation is in ELF format or similar format, which contains the target code run address. The run address is determined during link. When the debug program is downloaded, the program is downloaded to the specified address based on the address information in the ELF File. If the base address of Ram is set to 0x10000000 and the start address of firmware is set to 0x02000000 during compilation, the target code will be downloaded to 0x02000000, And the download will obviously fail.

All interruptions should be closed before the program is downloaded through JTAG, which is the same as the reason for disabling the Interruption During firmware initialization. When using the JTAG interface, the Enable of each interrupt is unknown, especially when an executable code exists in flash, and some interruptions may be enabled. When you use JTAG to download the code, the program may be interrupted because the initialization is not completed, leading to program exceptions. Therefore, you need to disable the interrupt first, generally by setting the SOC interrupt control register.

Use JTAG to write flash. Theoretically, JTAG can be used to access all devices on the CPU bus. Therefore, flash can be written. However, the writing method of Flash is very different from that of Ram and special commands are required, in addition, different flash erases have different programming commands, and the block size and quantity vary, making it difficult to provide this function. Therefore, debug generally does not provide the flash writing function, or only supports a few types of flash.

As I know, for ARM, only the FlashPGM software provides the FLASH writing function, but it is also very troublesome to use. Both axd and adw do not provide the FLASH writing function. When I wrote the Flash method, I wrote a simple program specifically used to write the FLASH of the target board. Using the JTAG interface, I downloaded the program to the target board, then, load the target code to be burned into the BIN format, and go down to the target board (the address is different from the address of the FLASH program), and run the downloaded FLASH program. This method seems faster than FlashPGM's Flash writing.

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