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1.2. Turn off the watchdog
The 1th chapter start. S detailed
1.2. Turn off the watchdog 1.2.1. Pwtcon intmod Intmsk Intsubmsk clkdivn
/* Turn off the watchdog *
/#if defined (config_s3c2400)
# define Pwtcon		0x15300000
# define INTMSK		0x14400008/	* Interupt-controller Base addresses */
# define CLKDIVN	0x14800014	* clock divisor Register *
/#elif defined (config_s3c2410) | | defined (config_s3c2440)
# define Pwtcon		0x53000000
# define Intmod		0x4a000004
# define INTMSK		0x4a000008/	* Interupt-controller Base addresses */
# define Intsubmsk	0x4a00001c
# define CLKDIVN	0x4c000014/	* Clock Divisor register *
/ #endif

The corresponding address of the above several macro definitions can be found in the corresponding datasheet:

Where the s3c2410 and TQ2440 boards use the CPU s3c2440, both in this part of the register definition, are the same, so here, using the definition of config_s3c2410.

About s3c2440 related hardware and software materials, this site provides a very comprehensive:

There are datasheet of s3c2440 CPUs:


There is a corresponding register definition:

Figure 1.3. Pwtcon

Figure 1.4. Intmod

Figure 1.5. Intmsk

Figure 1.6. Intsubmsk

Figure 1.7. CLKDIVN

For the specific meaning of each register, see the following analysis.

1.2.2. Ldr Pwtcon
#if defined (config_s3c2400) | | Defined (config_s3c2410) | | Defined (config_s3c2440)
	Ldr     r0, =pwtcon

LDR here and the LDR instructions described earlier are not meant to be.

The LDR here is the pseudo-Directive LDR.


Pseudo-directives, which are "pseudo" instructions, are for "true" instructions.

The real instructions are the common instructions, such as the arm's ldr,bic,msr and so on, which are the real instructions in the ARM architecture, and you find the corresponding meanings in the arm assembly instruction set.

and the pseudo-instruction is written to the assembler, the assembler can see the pseudo-directive specific expression of what the meaning, and then translate it into a real instruction or the corresponding processing.

Pseudo instruction Ldr syntax and meaning:


Another is the LDR pseudo-directive, although the LDR pseudo-directive and arm's LDR directive are very similar, but the function is not quite the same. LDR Pseudo-directives can be preceded by an immediate number = to indicate that an address is written to a register, such as:

Ldr R0, =0x12345678

In this way, the 0x12345678 address is written to the r0. Therefore, LDR Pseudo-instructions and MOV are more similar.

Only the immediate number behind the MOV instruction is limited, this immediate number, can have to be a 8-bit binary number, that is, a value within the 0x00-0xff, after an even number of right to get, this is the legitimate data, and LDR pseudo-directive does not have this restriction.

Then why is the operand of the LDR pseudo-instruction Unlimited, that is because it is a pseudo-directive, written out of the pseudo-instructions, will eventually be interpreted by the compiler into a real, legitimate instructions, and generally the corresponding MOV instructions.

In this case, to write the assembler, the use of MOV instructions is more troublesome, because some simple data is easier to see, some data is not easy to see whether it is legitimate data. So, to this, LDR pseudo-instructions appear, is to solve this problem, you just rest assured with the LDR pseudo-instructions, do not care about the operand, and write the LDR pseudo-instructions, the compiler will help you translate into the corresponding real assembly instructions.

And about how the compiler will translate these LDR pseudo-directives into a real assembly instructions, my understanding is that it will automatically calculate the corresponding operand, whether it is a legitimate MOV operand, if it is, will be the LDR pseudo-instructions translated into MOV instructions, otherwise, in other ways to deal with, I observed, One way is to apply a single 4-byte space to hold the operand, and then implement it with LDR instructions.

In Uboot, after the final make is finished, the U-boot is produced,


Arm-linux-objdump–d u-boot > Dump_u-boot.txt

The corresponding assembly code can be exported to the TXT file, where the pseudo-directive can be found:

Ldr     R0, =0x53000000

The corresponding, real assembly code:

33d00068:	e3a00453 	mov	r0, #1392508928	; 0x53000000

So it was translated into MOV instructions.

And after my attempt, deliberately changed 0x53000000 to 0x53000010, the corresponding production of the assembly code for:

33d00068:	e59f0408 	Ldr	r0, [pc, #1032]	; 33d00478 <fiq+0x58>
... 33d00478:	53000010 	. Word	0x53000010

It can be seen that because 0x53000010 is not a valid MOV operand, unable to find the right 0x00-0xff to go through an even number of cycles to the right, so can only be replaced here in this way, that is, in addition to the application of a word space to store this value:

33d00478:	53000010 	. Word	0x53000010

Then by calculating the relative current PC offset, get the address, with LDR instructions to remove the value of the address, that is, 0x53000010, to r0, compared to the MOV instructions, to more complex, but also consumes a word space.

Correspondingly, the other way, the personal understanding, seems can also through the mvn instruction to realize, the concrete detail, waits for further exploration.

And here's:

Ldr     R0, =pwtcon

The meaning is very clear, is to assign the value of the macro Pwtcon to the R0 register, that is,


1.2.3. mov
	mov     R1, #0x0

MOV instruction syntax:

1. mov instruction

The format of the MOV instruction is:

mov{condition}{s} destination register, source operand

The MOV instruction can be completed from another register, a shifted register, or an immediate number is loaded into the destination register. Where the S option determines whether the operation of the directive affects the value of the conditional flag bit in CPSR, and when no S is not updated the value of the conditional flag bit in CPSR.

instruction Example:

MOV r1,r0; Transfers the value of the register R0 to the Register R1

MOV pc,r14; Transfers the value of the register R14 to the PC, often used for subroutine return

MOV r1,r0,lsl#3; Transfers the value of the register R0 to the R1 after the left 3-bit shift

However, for the MOV instruction to say more, that is, generally can be used similar to:

MOV r0,r0

Instructions to implement NOP operations.

The above-mentioned MOV instruction is very simple, is to give the value of 0x0 to R1, that is


1.2.4. Str
	STR     R1, [R0]

STR instruction Syntax:

4. STR instruction

The format of the str instruction is:

str{condition} Source register,< memory address >

The str instruction is used to transfer a 32-bit word data from the source register to memory. The instruction is more commonly used in program design, and the way of addressing is flexible and varied, so it can refer to the instruction Ldr.

instruction Example:

STR r0,[r1],#8; Writes the word data in R0 to the R1-address memory, and

Writes the new address r1+8 to R1.

STR R0,[r1,#8]; writes the word data in R0 to R1+8-address memory.

So the function of STR is also very simple, that is, the value of the R1 register is transferred to the address value of R0 (memory) memory.

In C language, it means:

*r0 = R1

So the above lines of code are very clear:

First, using the R0 register to store the value of Pwtcon, and then r1=0, and then write 0 R1 in Pwtcon, in fact, is

Pwtcon = 0;

And what is the specific meaning of the Pwtcon register? Here's a look at the detailed meanings:

Figure 1.8. Bit field of the Wtcon register

Notice that bit[0] is reset enable/disable, and set to 0, that is to turn off the reset of watchdog, so the other bit configuration options, it is not necessary to see.

All we need to know is that the watchdog watchdog (reset function) is banned here.

For the role of the watchdog and why to turn off the watchdog when the system is initialized, see the section later in this document: Section 3.3, "What is watchdog + why shut down watchdog at system initialization"

The 1th chapter start. S detailed 1.3. Turn off interrupts

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