Details of MII, rmii, and gmii Interfaces

Overview:

Media independent interface (media-independent interface), or media-independent interface, is the Ethernet industry standard defined by the IEEE-802.3. It includes a data interface and a management interface between MAC and PHY.

Data interfaces include two independent channels used for the transmitter and receiver respectively. Each channel has its own data, clock, and control signal. The MII data interface requires a total of 16 signals.

The management interface is a dual-signal interface: one is the clock signal, and the other is the data signal. Through the management interface, the upper layer can monitor and control the phy. The MII (Management Interface) has only two signal lines.
The MII standard interface is used to connect Fast Ethernet MAC-block and PHY. It indicates that, without re-designing or replacing the Mac hardware, any type of PHY device can work normally. Interfaces working at other speeds are equivalent to MII: AuI (10 M Ethernet), gmii (Gigabit Ethernet), and xaui (10-Gigabit Ethernet ).
MII Bus
The MII bus specified in 802.3 is a universal bus used to connect different types of PHY to the same network controller (MAC. The network controller can use the same hardware interface to connect to any Phy.

Introduction to MII interfaces:
Ethernet Media interfaces: MII rmii smii gmii
All these interfaces come from MII. The MII (medium independent interface) means that the media is copper axis, optical fiber, cable, etc, this is because all of these media processing tasks are completed by the phy or Mac chip.
MII supports operations of 10 m and 100 m. An interface consists of 14 lines. Its support is flexible, but there is a disadvantage that it uses too many signal lines for a port, if a vswitch with eight ports needs 112 lines, port 16 requires 224 lines, and port 32 requires 448 lines. Generally, a vswitch is created based on this interface, it is not realistic, so modern switch production will use other standards simplified from MII, such as rmii, smii, and gmii.
Rmii is a simplified MII interface. In terms of data sending and receiving, it is twice the signal line of the MII interface, so it generally requires a 50 MB bus clock. Rmii is generally used in a multi-port switch. Instead of sending and receiving two clocks for each port, a clock is used for sending and receiving all the data ports, this reduces the number of ports. One rmii port requires seven data lines, which is twice less than MII, so the switch can access multiple data ports. Like MII, rmii supports 10 m and 100 M Bus Interface speeds.
Smii is a media interface proposed by Cisco. It has fewer signal lines than rmii, and s indicates serial. Because it only uses one signal line to transmit data and one signal line to transmit and receive data, in order to meet the requirement of 100, the clock frequency is very high, reaching 125 MB, why is 125 MB used? It is because some control information is transmitted in the data line. Smii only uses four signal lines to transmit 100 signals on one port, which is almost twice as short as rmii. Smii is strongly supported in the industry. Similarly, data transmission and receiving on all ports share the same external M clock.
Gmii is the MII interface of gigabit network, which also has the corresponding rgmii interface, indicating the simplified gmii interface.

How MII works:
"Media Independence" indicates that any type of PHY device works properly without re-designing or replacing the Mac hardware. Two independent channels are used for the transmitter and receiver respectively. Each channel has its own data, clock, and control signal.
The MII data interface requires a total of 16 signals, including tx_er, txd, tx_en, tx_clk, Col, rxd, rx_ex, rx_clk, CRS, and rx_dv.
MII transmits data in four-byte bidirectional transmission with a clock rate of 25 MHz. The working rate can reach 100 Mb/s.
The MII management interface is a dual-signal interface. One is a clock signal and the other is a data signal.
Through the management interface, the upper layer can monitor and control the phy, and its management is done by using the SMI (Serial Management Interface) bus by reading and writing the register of the phy.
Some registers in the PHY are defined by IEEE. In this way, the PHY reflects its current status to the Register, mac constantly reads the Status Register of the PHY through the SMI bus to get the current PHY status, such as connection speed and duplex capability.
Of course, you can also set the register of the PHY through SMI to achieve the purpose of control. For example, if the throttling is enabled or disabled, the self-negotiation mode or the forced mode can be used.
Both the MII bus for physical connection and the State registers and control registers for the SMI bus and the PHY have IEEE specifications. Therefore, the Mac and the PHY of different companies can coordinate their work. Of course, in order to match the features specific to PHY of different companies, the driver needs to be modified accordingly.
Phy is a physical interface transceiver that implements the physical layer. Including the MII/gmii (Media independent interface) Sub-layer, PCs (physical encoding sub-layer), PMA (physical media attachment) Sub-layer, PMD (physical media-related) Sub-layer, and MDI sub-layer. 100basetx adopts 4b/5b encoding.
When sending data, phy receives data from MAC (for phy, there is no frame concept, and for it, it is data regardless of the address, data or CRC ), an Error Code of 1 bit is added for every 4 bits. Then, parallel data is converted into serial stream data, and the data is encoded according to the encoding rules of the physical layer. Then, the data is sent as a analog signal. Otherwise.
Another important feature of PHY is to implement some CSMA/CD functions.
It can detect whether data is being transmitted on the network. If data is being transmitted, it waits. Once it detects that the network is idle, it waits for a random time and sends the data out. If the two send data at the same time, a conflict will occur. At this time, the conflict detection agency can detect the conflict and wait for a random time to resend the data. This random time is very exquisite. It is not a constant. The random time calculated at different times is different, there are multiple algorithms to cope with the second conflict between the two hosts with low probability.
The communication rate is negotiated by both parties. The negotiation result is the maximum speed and the best duplex mode supported by both devices. This technology is called auto negotiation or Nway.
The isolating transformer filters the differential signals sent from the PHY using the differential mode coupled coils to enhance the signal, and couple the signals to the other end of the connected network through the electromagnetic field conversion.
In the RJ-45, 1, 2 are the data, and 3, 6 are the data.
The new PHY supports auto MDI-X and also requires isolating transformer support, it can realize the transfer signal line on 1 and 2 of RJ-45 interface and the function of receiving signal line on 3 and 6 automatically exchange with each other.

Gmii introduction:
Gmii (Gigabit MII)
Gmii uses eight-bit interface data with a 125 MHz clock, so the transmission rate can reach 1000 Mbps. It is also compatible with the MII 10/100 Mbps working mode.
The gmii interface data structure complies with the IEEE Ethernet standard. For the interface definition, see IEEE 802.3-2000.
Transmitter:
◇ Gtxclk -- the clock signal of the guitar TX .. signal (125 MHz)
◇ TXCLK--10/M signal clock
◇ Txd [7 .. 0] -- sent data
◇ Txen-transmitter enabling Signal
◇ Txer -- transmitter error (used to destroy a data packet)
Note: gtxclk signals are provided to PHY at a gigabit rate. txd, txen, and txer signals are synchronized with these clock signals. Otherwise, at a rate of 10/100 M, phy provides the txclk clock signal, and other signals are synchronized with this signal. The operating frequency is 25 MHz (2.5 m Network) or MHz (10 m network ).
Receiver:
◇ Rxclk -- receives the clock signal (extracted from the received data, so it is not associated with gtxclk)
◇ Rxd [7 .. 0] -- receives data
◇ Rxdv -- receive valid data indication
◇ Rxer -- receive Data Error Indication
◇ Col-conflict detection (for half duplex only)
Manage configurations
◇ MDC -- configure the interface clock
◇ Mdio -- configure the interface I/O
Manage the configuration interface to control the features of the phy. This interface has 32 register addresses, each of which is 16 bits. Among them, the first 16 have defined the purpose in "IEEE 802.3, 2000-22.2.4 management functions", and the remaining are designated by each device.

 

Rmii introduction:
Rmii: The reduced media independant interface simplifies the independent media interface. It is one of the standard Ethernet interfaces and has less I/O transmission than MII.
Questions about rmii and MII
The rmii port uses two wires to transmit data,
The MII port uses four wires to transmit data,
Gmii uses eight wires to transmit data.
MII/rmii is only an interface. For 10 m wire speed, the MII speed is 2.5 m, and rmii is 5 M. For M wire speed, the MII speed is 25 m, rmii is 50 m.
MII/rmii is used to transmit Ethernet packets. The MII/rmii interface is 4/2bit. In the Ethernet phy, serial conversion and encoding/decoding are required to transmit packets on twisted pair wires and optical fiber cables, the frame format complies with IEEE 802.3 (10 m), IEEE 802.3u (100 m), and IEEE 802.1Q (VLAN ).
The format of the Ethernet frame is: prefix + start bit + Destination MAC address + source MAC address + type/Length + Data + padding (optional) + 32 bitcrc
If a VLAN exists, a two-byte VLAN tag is added after the type/length. 12 bits represent the vlan id, and 4 bits represent the data priority!

 

Network Card working principle, Mac and PHY:

We know the network card, one of the essential components for accessing the Internet.

The network adapter works on the last two layers of OSI. The physical layer and the data link layer define the electrical and optical signals, line statuses, clock benchmarks, data encoding, and circuits required for data transmission and reception, provides standard interfaces to data link layer devices. The Physical Layer Chip is called Phy. The data link layer provides addressing mechanisms, data frame construction, data error check, transfer control, and standard data interfaces to the network layer. The data link layer chip in the ethernet card is called the Mac controller. Many NICs work together. The relationship between them is that the PCI bus is connected to the Mac bus, the Mac is connected to the phy, And the PHY is connected to the network cable (of course, it is not directly connected, there is also a pressure change device ).

Next, let's take a look at how data is transmitted and communicated between PHY and Mac. Connect Mac and PHY through the standard MII/gigamii (Media independed interfade) interface defined by IEEE. This interface is defined by IEEE. The MII interface controls all the data and data on the network. Mac determines the operating status of the PHY and controls the PHY by using the SMI (Serial Management Interface) interface to read and write the register of the phy. Some registers in the PHY are also defined by IEEE. In this way, the PHY reflects its current status to the Register, mac constantly reads the Status Register of the PHY through the SMI bus to get the current PHY status, such as connection speed and duplex capability. Of course, you can also set the register of the PHY through SMI to achieve the purpose of control. For example, if the throttling is enabled or disabled, the self-negotiation mode or the forced mode can be used. We can see that both the MII interface of physical connection and the status registers and control registers of SMI bus and PHY have IEEE specifications. Therefore, Mac and PHY of different companies can coordinate their work. Of course, in order to match the features specific to PHY of different companies, the driver needs to be modified accordingly. The implementation of the main functions of a NIC is basically the above. In addition, there is an EEPROM chip, usually a 93c46 chip. It records the NIC chip supplier ID, subsystem supplier ID, Nic MAC address, Nic configurations, such as the PHY address on the SMI bus and bootrom capacity, whether to enable the bootrom boot system. Many NICs also have bootrom. It is used to boot the operating system with a diskless workstation. Since there is no disk, some of the programs and protocol stacks necessary for boot are put in it, such as RPL and PXE. In fact, it is a standard PCI Rom. Therefore, some hard disk write protection cards can be implemented by burning the bootrom of the NIC. In fact, the ROM of the PCI device can be placed in the BIOS of the motherboard. The ROM can be detected and correctly identified when the computer is started. The configuration of AGP is the same as that of PCI in many places. Therefore, the BIOS of many graphics cards can also be placed in the BIOS of the motherboard. This is why we have never seen bootrom for onboard NICs.

2. In the working process, when sending data, phy receives MAC data (for phy, there is no frame concept, and for it, it is data regardless of the address, the data is still CRC). Each 4-bit is added with a 1-bit check error code. Then, parallel data is converted to serial stream data, and then encoded according to the physical layer rules (10based-t NRZ encoding or 100based-t Manchester encoding) encode the data and convert it into a simulated signal to send the data. Otherwise. Now let's take a look at the following part of the output of Phy. When a CMOS chip is working, the signal level is always greater than 0 V (depending on the chip's process and design requirements ), however, if such a signal is sent to a location of 100 meters or longer, there will be a great loss of DC components. In addition, if the external network is directly connected to the chip, electromagnetic induction (Thunder) and static electricity can easily cause damage to the chip. In addition, if the grounding method of the device is different, the power grid environment may cause the 0 V levels of both parties to be inconsistent. In this way, the signal is transmitted from A to B because the 0 V level of the device is different from the 0 V level of the B point, this will lead to a large amount of current flowing from devices with high potential to devices with low potential. How can we solve this problem? The transformer (isolating transformer) device appears. It filters the differential signals sent by PHY with the difference mode coupled coil to enhance the signal, and is coupled to the other end of the connected network cable through the electromagnetic field conversion. In this way, not only does the network cable and the PHY have no physical connection, but the signal is transferred instead, the DC component in the signal is cut off, and data can be transmitted in devices of different 0 V levels. The isolating transformer is designed to withstand 2kv ~ 3kv voltage. It also plays a role in Lightning Protection (I personally think it is inappropriate to use lightning protection. Some of my friends' network devices are easily burned out during thunderstorms. Most of them are caused by unreasonable PCB design, and most of them burn down the interfaces of the devices, with few chips burned out, isolation transformer plays a protective role.