Development notes-NAND Flash addressing mode

I wrote it very early. I used it to collect the number first.

The addressing mode of NAND Flash is closely related to the memory mode of NAND Flash. The data of NAND Flash is
Bit is stored in memory cell. Generally, only one bit can be stored in a cell. These cells are composed of eight
Or 16 are in the unit of bit line to form the so-called byte (X8)/Word (x16), which is the NAND device's
Bit Width.
These lines form a page, usually 528 Bytes/page or 264 word/page. Then, every 32 pages are formed.
One block, sizeof (Block) = 16 Kbyte
Block is the largest operating unit in NAND Flash, and the erasure is completed in the unit of block.
Programming/reading is performed in the unit of page.
Therefore, the following three types of addresses can be formed according to the organization method:
-Block address
-Page address
-Column address
First, it must be clear that for NAND Flash, the address and command can only be passed on I/O [], and the data width
It can be 8-or 16-bit. However, for x16 NAND devices, I/O [] is only used to transmit data. Clear this
One point, we can start to analyze the addressing mode of NAND Flash.
-> Take a 528 byte/Page NAND device with a total capacity of 512 Mbit + 512kbyte as an example:
Because 1 block = 16 Kbyte, 512 Mbit = 64 Mbyte, numberof (Block) = 1024
1 block = 32 page, 1 page = 528 byte = 512 byte (main area) + 16 byte (spare Area)
User data is stored in main area.
9bit is required for 512byte. For the 528byte series nand, The 512byte is divided into 1st half and 2nd half,
Each access is selected by the so-called pointer operation command, that is, bit8. So A8 is
Halfpage pointer (this is a name I have given). A [] is the so-called column address.
32 pages must be expressed in 5 bits, occupying a [], that is, the relative address of the page in the block.
The block address is represented by BITs above A14, such as 4096 MB nand, with a total of blocks. Therefore, 12 bits are required.
A []. If it is a 528 byte/Page NAND flash of 1gbit, block address is used
A [26:24] indicates. While page address is blcok address | PAGE address in Block
The address of NAND Flash is:
Block address | PAGE address in block | halfpage pointer | column address
The address transfer sequence is column address, page address, and block address.
Because the address can only be transmitted on I/O [], it must be shifted.
For example, for 512 Mbit X8 NAND Flash, the address range is 0 ~ 0x3ff_ffff, as long as it is a value in this range
The addresses are valid.
Take nand_addr as an example:
The second step is to pass the column address, that is, nand_addr [], which can be passed to I/O [] without shift.
Halfpage pointer, that is, bit8, is determined by the Operation Command, that is, the command determines on which halfpage to read and write,
The true bit8 value is don't care.
Step 2: Shift nand_addr to 9 places right and upload nand_addr [] to I/O [].
Put nand_addr [] on I/O in step 2.
Step 2: Place nand_addr [25] On I/O.
Therefore, the entire address delivery process can be completed in four steps, namely 4-step addressing.
If the NAND Flash capacity is less than Mbit, the maximum bit of block Adress is only bit24, so addressing
Only three steps are required.

Next, we will give a brief description of the x16 NAND flash device.
Because the size of the main area of a page is 256 word, it is still equivalent to 512 bytes. However
1st halfpage and 2nd halfpage. Therefore, bit8 becomes meaningless.
Bit8 is completely unnecessary, and the address transmission is still the same as that of the X8 device. In addition, x16's NAND usage and
X8 is used in the same way.

Written on Mar 17,2004
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