Differences and relationships between registers, triggers, and latches

Registers are generally edge-triggered triggers, which are called register in the circuit, and the triggers are the two types of logic gates, including level-triggered and edge-triggered, the latches are level-triggered. So generally, we only call registers and latches. In time series circuits, registers are used to transmit data only on the edge of the clock (Setup Time and hold time are sufficient ), the latches can transmit data at all effective level devices.

Register: Register, triggered by the clock edge. Generally, it is master-slave. We have learned this digital circuit mainly composed of a transport gate and a reverser. It is widely used!
Latch: latch, triggered by a level. There are many types of latch, including JK and RS in our digital circuits. Generally, it is composed of a transmission door and a reverser, the advantage is that the area is small, but timing analysis is difficult!
A trigger generally refers to a register: Flip-flop

 

D. What is the non-Q level when the trigger is powered on?

D. The trigger is not fixed. It is only known when there is feedback. RC delay circuits can be added to R and S ends to pre-fabricate the initial state.

 

 

Latches

 

In a real digital system, the synchronous time series logic circuit that can be used to store a set of binary code is usually called a register. Because the trigger has a memory function, the trigger can easily form a register. Since a trigger can store one binary code, connecting the clock ports of N triggers can constitute a register for storing n binary codes. A latch is a level-triggered storage unit. The data storage action depends on the level value of the input clock (or enable) signal, the output changes with the data input.

 

Trigger

A trigger is an edge-sensitive storage unit. The data storage action synchronizes the rising or falling edges of a signal. In a real digital system, the synchronous time series logic circuit that can be used to store a set of binary code is usually called a register. Because the trigger has a memory function, the trigger can easily form a register. Since a trigger can store one binary code, connecting the clock ports of N triggers can constitute a register for storing n binary codes. Registers are used to store some small storage areas of data and temporarily store the data involved in calculation and calculation results. In fact, registers are a commonly used time series logic circuit, but this time series logic circuit only contains the storage circuit. The storage circuit of registers is composed of latches or triggers. Because a latch or trigger can store 1-bit binary numbers, N latches or triggers can form N-bit registers.
A trigger locks data along the clock, while a latch uses a level to enable data storage. Therefore, the Q output end of the trigger will be updated on every clock edge, and the latch can be updated only when the Enable level is effective.
Some textbooks use latches for triggers. In FPGA design, we recommend that you use triggers instead of latches if not necessary.

The clock control D trigger is actually a d lock, and the edge D trigger is the real D Trigger. When the clock control D trigger is enabled, the output changes with the input, edge triggers are output only when the edge jumps. Two d latches can form a D Trigger. In the final analysis, DFF is edge-triggered, while latch is level-triggered. The output of the latches is transparent to the input, what the input is, and what the output is. This is why the latches are unstable, and the trigger is a master-slave trigger consisting of two latches, the output is not transparent to the input. The input must be reflected in the output only when the clock goes up/down. Therefore, the input glitch signal can be eliminated.

Comparison between triggers and latches:
1. latch is triggered by the level and is not controlled synchronously. When the enable signal is valid, latch is equivalent to the path. When the enable signal is invalid, latch maintains the output state. DFF is triggered by the clock edge for synchronous control.
2. latch is sensitive to the input level and is greatly affected by the wiring delay. It is difficult to ensure that the output is not burrs. DFF is not easy to generate burrs.
3. If the door circuit is used to build latch and DFF, latch consumes less door resources than DFF, which is a better place for latch than DFF. Therefore, the integration of latch in ASIC is higher than that of DFF, but the opposite is true in FPGA, because there is no standard latch unit in FPGA, but there is a DFF unit, A latch can be implemented only by multiple le. Latch is a Level Trigger, which is equivalent to an enabling end. After activation (when enabling the level), it is equivalent to a wire and changes with the output. In the non-enable state, the original signal is maintained, which shows the difference with flip-flop. In fact, latch cannot replace FF in many cases.
4. Latch makes static timing analysis extremely complex.

5. latch is currently only used in extremely high-end Power channels, such as Intel's P4 CPU. If FPGA has a latch unit, the Register unit can be configured as a latch unit. In the Xilinx v2p manual, the Unit can be configured as a register/LATCH unit. The attachment is the structure of Xilinx half slice.

The general design rule is to avoid latch in most designs. It will make the timing sequence of your design end, and its concealment is very strong, it cannot be found by a veteran. Latch does not filter burrs. This is extremely dangerous for the next-level circuit. Therefore, as long as the D trigger can be used, latch is not needed.
In some cases, there is no clock, and you can only use latch. For example, if a CLK is used to connect to the latch enable end (assuming a high-level enable), the setup time is the time required before the data drops along the clock, however, if it is a DFF, the setup time is the time required for the rising edge of the clock. This means that if the data is later than the control signal, only latch can be used. In this case, the latch timing borrow mentioned above is used. Basically, it is equivalent to borrowing a high-level time. That is to say, latch borrow time is also limited.

The STA analysis on latch is actually acceptable, but you must be familiar with the tool. however, errors are very easy. currently, primetime supports latch analysis. the built-in Stas analysis functions of some integrated tools are also supported, such as RTL compiler and Design Compiler. in addition to ASIC, resources can be saved. Latch may be quite small in the synchronous design. Now, it is usually put in FF during the processing.