Differences between ARM commands and thumb commands

I. Differentiate the arm instruction set from the thumb Instruction Set first.
The thumb command can be seen as a subset of arm commands in the form of compression. It is proposed for the code density problem. It has 16-bit code density, but it is not as efficient as arm commands. thumb is not a complete architecture. It cannot expect processing to only execute thumb instructions, but does not support arm instruction sets. therefore, the thumb command only needs to support general functions. If necessary, you can use a complete arm instruction set. For example, all exceptions automatically enter the arm status. when writing the thumb command, you must first use the pseudo command code16 Declaration, and in the arm command, you must use the Bx command to jump to the thumb command to switch the processor status. when writing arm commands, you can use the pseudo command code32 to declare.

Pipeline processing:
Unlike the micro-coding processor, arm (keeping it of a high-performance nature) is completely hardwired.

A three-phase pipeline is used to accelerate the execution of arm 2 and arm 3. The first stage holds the instruction retrieved from the memory. The second stage starts decoding, while the third stage actually executes it. Therefore, the program counter always exceeds the two commands currently executed. (This parameter must be included when calculating the offset for the branch command ).

Because of this pipeline, two command cycles are lost at the branching (because the pipeline needs to be fully added ). Therefore, it is best to use conditional execution commands to avoid wasting cycles. For example:

...
CMP r0, #0
Beq over
MoV R1, #1
MoV R2, #2
Over
...

It can be written as more effective:
...
CMP r0, #0
Movne R1, #1
Movne R2, #2

Ii. Differences between thumb instruction sets and arm Instruction Sets
The thumb instruction set does not contain coprocessor instructions, semaphores commands, CPSR or spsr access instructions, multiplication instructions, 64-bit multiplication instructions, and the second operand of commands is limited; except for the conditional execution function of redirect command B, all other commands are executed unconditionally. Most thumb data processing commands adopt the 2-address format. the differences between thumb Instruction Set and arm instruction set are as follows:
Jump command
Programs are relatively transferred. In particular, the conditional jump has more restrictions than the redirection in arm code, and the redirection subroutine is unconditional.
Data processing commands
Data processing commands operate on General registers. In most cases, the operation results must be put in one of the operand registers, rather than the other 3rd registers. less data processing operations than arm status, access register R8 ~ R15 is subject to certain restrictions. In addition to the mov and add command accessors R8 ~ Other data processing commands except R15 always update the ALU status flag in CPSR. access register R8 ~ The thumb Data Processing Instruction of R15 cannot update the ALU status flag in CPSR.
Single Register loading and storage commands
In the thumb state, the single register loading and storage commands can only access the registers R0 ~ R7
Batch register loading and storage commands
The LDM and STM commands can set any range to R0 ~ The stack instruction R13 is used as the base address for loading or storing the. Push and pop commands in the subset of R7 registers to implement full decreasing of stacks ~ In addition to R7, the push command can also store the link register R14, And the pop command can load the program instruction PC

Arm commands are divided into the following types:

I. Arm memory access commands
Operator condition Code Location
LDR Rd, addressing loading word data RD Direction [addressing], addressing index LDR {cond}
Ldrb Rd, addressing load the unoperator byte data RD bytes [addressing], addressing index LDR {cond} B
Ldrt RD and addressing load the word data in user mode: RD Direction [addressing] and addressing index LDR {cond} t
Ldrbt Rd, addressing loads the unsigned word data in user mode. RD region [addressing], addressing index LDR {cond} Bt
Ldrh Rd, addressing load the unsigned half-word data RD using [addressing], addressing index LDR {cond} H
Ldrsb Rd, addressing loaded with the byte data RD Direction [addressing], addressing index LDR {cond} sb
Ldrsh Rd, addressing loaded with the operator's half-character data RD Direction [addressing], addressing index LDR {cond} sh
STR Rd, addressing stores word data [addressing] ← Rd, addressing index STR {cond}
Strb Rd, addressing stores byte data [addressing] ← Rd, addressing index STR {cond} B
Strt Rd, addressing stores word data in user mode [addressing] ← Rd, addressing index STR {cond} t
Srtbt Rd, addressing stores byte data in user mode [addressing] ← Rd, addressing index STR {cond} Bt
Strh Rd, addressing stores semi-word data [addressing] ← Rd, addressing index STR {cond} H
LDM {mode} rn {!}, Reglist batch (Register) Loading reglist records [Rn…], Rn back-to-memory LDM {cond} {more}
STM {mode} rn {!}, Rtglist batch (Register) storage [Rn…] Optional reglist, RN, etc. stm {cond} {more}
SWP Rd, RM, RN register and memory word data exchange RD branch [RD], [Rn] register [RM] (Rn = RD or RM) SWP {cond}
Swpb Rd, RM, RN register and memory byte data exchange RD records [RD], [Rn] records [RM] (RN =rd or RM) SWP {cond} B

2. Arm data processing commands
Operator condition Code Location
MoV Rd, operand2 data transfer RD operator operand2 mov {cond} {s}
MVN Rd, operand2 data is not transferred RD partition (operand2) MVN {cond} {s}
Add Rd, RN operand2 addition operation command RD limit rn + operand2 add {cond} {s}
Sub Rd, RN operand2 subtraction operation command RD minus Rn-operand2 sub {cond} {s}
RSB Rd, RN operand2 reverse subtraction command RD minus operand2-Rn RSB {cond} {s}
ADC Rd, RN operand2 inner addition RD 127rn + operand2 + carry ADC {cond} {s}
SBC Rd, RN operand2 bringing the bitwise subtraction command RD minus Rn-operand2-(not) carry SBC {cond} {s}
RSC Rd, RN operand2 bringing backward subtraction instruction RD minus operand2-Rn-(not) carry RSC {cond} {s}
And Rd, RN operand2 logic and Operation Command RD 127rn & operand2 and {cond} {s}
ORR Rd, RN operand2 logic or operation command RD limit rn | operand2 Orr {cond} {s}
EOR Rd, RN operand2 logical XOR or operation command RD limit rn ^ operand2 EOR {cond} {s}
Bic Rd, RN operand2 bits clear command RD employee rn &(~ Operand2) Bic {cond} {s}
Cmp rn, operand2 comparison command mark n, Z, C, V indication Rn-operand2 CMP {cond}
Comparison of negative numbers of CEN Rn AND operand2 command marks N, Z, C, V jwrn + operand2 CEN {cond}
Tst RN, operand2 test command mark n, Z, C, V jwrn & operand2 TST {cond}
Teq rn, operand2 equal test command mark n, Z, C, v limit rn ^ operand2 TEQ {cond}

Iii. Multiplication instructions
There are 32 × 32 multiplication instructions, 32 × 32 multiplication and addition instructions, 32 × 32 results are 64-bit multiplication/Multiplication instructions.
Operator condition Code Location
Mul Rd, RM, RS 32-bit multiplication command RD 1_rm * RS (RD =rm) Mul {cond} {s}
MLA Rd, RM, RS, RN 32-bit multiplier command RD ready RM * Rs + rn (RD =rm) MLA {cond} {s}
Umull rdlo, rdhi, RM, RS 64-bit unsigned multiplication command (rdlo, rdhi) limit RM * Rs umull {cond} {s}
Umlal rdlo, rdhi, RM, RS 64-bit unsigned multiplication and addition command (rdlo, rdhi) using RM * Rs + (rdlo, rdhi) umlal {cond} {s}
Smull rdlo, rdhi, RM, RS 64-Bit Signed multiplication command (rdlo, rdhi) limit RM * Rs smull {cond} {s}
Smlal rdlo, rdhi, RM, RS 64-Bit Signed multiplication and addition command (rdlo, rdhi) using RM * Rs + (rdlo, rdhi) smlal {cond} {s}

Iv. Jump commands
There are two methods to achieve program jump in arm. One is to use Jump commands to directly jump, and the other is to directly assign values to PC registers to achieve jump.

Operator condition Code Location
B label jump command PC terminal Label B {cond}
BL label jump command LR ← PC-4 with Link, PC ← label BL {cond}
Bx rm jump command PC terminal label with status switch, switch processing status BX {cond}

5. Arm coprocessor commands
Arm supports coprocessor operations. The coprocessor control must be implemented through coprocessor commands.
Operator condition Code Location
CDP
Coproc, opcodel, CRD, CRN, CRM {, opcode2} coprocessor data operation instructions depend on coprocessor CDP {cond}
LDC {L} coproc, CRD <address> the coprocessor data read instruction depends on the coprocessor LDC {cond} {L}
STC {L} coproc, CRD, <address> the coprocessor Data Writing Instruction depends on the coprocessor STC {cond} {L}
Arm registers to coprocessor
The data transfer instructions for MCR coproc, opcodel, RD, CRN, {, opcode2} registers depend on the co-processor MCR {cond}
Coprocessor register to arm
MRC coproc, opcodel, RD, CRN, {, opcode2}

V. Arm miscellaneous commands
Operator condition Code Location
SWI immed_24 Soft Interrupt command causes Soft Interrupt, processor enters management mode SWI {cond}
The read Status Register command of Mrs RD and SRS is RD ready. The value of this command is CPSR or spsr. The value of this command is Mrs {cond}
MSR psr_fields, RD/# immed_8r write Status Register command psr_fields initrd/# immed_8r, And the SRs are CPSR or spsr MSR {cond}