Differences between ARM7 and ARM9.

ARM7 Series Processors are the mainstream embedded processors designed by arm companies in the UK.
The ARM7 kernel is a three-level assembly line of 0.9 MIPS/MHz and a Von noiman structure;
The arm9-kernel is a 5-level assembly line that provides a 1.1 MIPS/MHz Harvard structure.
Arm720t is MMU, arm9tdmi, arm9tdmi, ARM9E-S and other series arm99 are MMU, arm940t only memory Protection Unit. Not a complete MMU.
The clock frequency of ARM is higher than that of arm. It uses the Harvard structure to distinguish between the data bus and the command bus. The ARM processor uses a three-level pipeline, while the arm uses a five-level pipeline, the five-level pipeline can allocate each instruction processing time to five clock cycles, and five commands are executed simultaneously in each clock cycle. In the same processing technology, the clock frequency of the arm9tdmi processor is 1.8 ~ 2.2 times. Command cycle improvement,
Command cycle improvement:
2.1 loads command spear n stores command
The most obvious improvement of the number of instruction cycles is the loads and stores commands. The execution time of these two commands is reduced by 30% from ARM7 to ARM9. The reduction of the instruction cycle is caused by the difference in the two basic micro-processing structures in the ARM7 and ARM9.
(1) arm9-has an independent instruction and data storage interface, allowing the processor to read and write data at the same time. This is called the improved Harvard structure. However, ARM7 only has a data storage interface, which is used for command and data access at the same time.
(2) Level 5 pipelines introduce Independent memory and write-back pipelines for accessing memory and writing results back registers respectively.
The preceding two points implement the loads and stores commands in one cycle.
2.2 interlocks Technology
Pipeline locks are generated when the data required by the command is not ready because the previous command has not been executed. When the pipeline locks, the hardware stops executing this command until the data is ready. Although this technology will increase Code Execution time, but it provides great convenience for early designers. Compiler and assembly Program You can redesign the code sequence or other methods to reduce the number of mutual locks in the pipeline.
2.3 branch commands
The Branch instruction cycles of ARM9. In addition, arm9tdmi and ARM9E-S do not predict the branch instruction.
Structure and features of ARM9.
Taking ARM9E-S as an example, the main structure and characteristics of arm9-processor are introduced.
(1) 32-Bit fixed-point Proteus processor, improved ARM/thumb code intertwined, enhanced Multiplier Design. Supports real-time debugging;
(2) In-chip commands and data SRAM, and the memory capacity of commands and data can be adjusted;
(3) In-chip instruction and Data High-speed buffer (cache) capacity from 4 K bytes to 1 M bytes;
(4) setting a protection unit (protcction unit) is very suitable for storing segments and protection in embedded applications;
(5) use the amba ahb Bus interface to provide a unified address and Data Bus for peripherals;
(6) support for external coprocessor, and support for simple handshake signaling between commands and data bus;
(7) supports standard basic logic unit scanning testing methodology and BIST (built-in-self-test );
(8) Support for Embedded macro tracking units and real-time tracking of commands and Data