Differences between FPGA and CPLD

From: http://tvb2058.spaces.eepw.com.cn/articles/article/item/15358

 

Although FPGA and CPLD are both programmable ASIC devices with many common features, the differences between CPLD and FPGA have their own characteristics:
① CPLD is more suitable for completing various algorithms and logic combinations, while fp ga is more suitable for completing time series logic. In other words, FPGA is more suitable for the rich structure of triggers, while CPLD is more suitable for the structures with limited and rich product items of triggers.
② The continuous cabling structure of CPLD determines that its timing delay is even and predictable, while the phased cabling structure of FPGA determines the unpredictability of Its latency.

③ FPGA is more flexible than CPLD in programming. CPLD is programmed by modifying the Logic Functions of a fixed internal connection circuit. FPGA is programmed by changing the wiring of internal connections. fp ga can be programmed under a logic gate, CPLD is programmed under the Logical Block.

④ FPGA is more integrated than CPLD and has more complex wiring structure and logic implementation.

⑤ CPLD is more convenient to use than FPGA. The programming of CPLD adopts E2PROM or FASTFLASH technology, which does not require external memory chips and is easy to use. The FPGA programming information needs to be stored in external memory, which is complicated to use.

⑥ CPLD is faster than FPGA and has a greater time predictability. This is because FPGA is a gate-level programming, and CLB adopts distributed interconnection, while CPLD is a logic block-level programming, and the interconnection between logical blocks is a general set.

7. In programming mode, CPLD is mainly based on E2PROM or FLASH memory programming, with a programming frequency of up to 10 thousand times. The advantage is that programming information is not lost when the system is powered off. CPLD can be divided into programming on the programmer and system programming. FPGA is mostly programmed based on SRAM. The programming information is lost when the system is powered off. During each power-on, the programming data needs to be re-written to the SRAM from outside the device. Its advantage is that it can be programmed at any time, and can be quickly programmed at work to achieve dynamic configuration at the board level and system level.

⑧ CPLD provides good confidentiality and poor FPGA confidentiality.

In general, the power consumption of CPLD is larger than that of FPGA, and the higher the integration level, the more obvious.

With the increase in the density of Complex Programmable Logic Devices (CPLD), digital device designers are flexible and easy to design, and their products can quickly enter the market. Many designers have seen the advantages of CPLD being easy to use, time sequence predictable, and high speed. However, in the past, due to the limitations of CPLD density, they had to turn to FPGA and ASIC. Now, designers can experience the benefits of CPLD with a density of up to 100,000.

The CPLD structure uses 1 to 16 product items in a logical path, so the running speed of large and complex designs can be predicted. Therefore, the operation of the original design can be predicted and reliable, and it is easy to modify the design. CPLD is flexible in nature, simple in sequence, and excellent in routing performance. Users can change their design while keeping pin output unchanged. Compared with FPGA, CPLD has more I/O and smaller size.

Nowadays, communication systems use many standards, and devices must be configured according to customer needs to support different standards. CPLD allows devices to make adjustments to support multiple protocols and change functions as standards and protocols evolve. This brings great convenience to system designers, because they can design hardware before the standards are fully mature, and then modify the code to meet the requirements of the final standards. The speed and delay characteristics of CPLD are better than pure software solutions. Its NRE cost is lower than ASIC, more flexible, and products can enter the market more quickly. The advantages of the CPLD programmable scheme are as follows:
● Rich logic and storage resources (Cypress Delta39K200 has more than 480 Kb of RAM)
● Flexible time series model with redundant routing resources
● Flexible output of changed pins
● It can be installed on the system and re-programmed
● Large I/O count
● Integrated memory control logic with Guaranteed Performance
● Single-Chip CPLD and programmable PHY Solutions
With these advantages, design modeling costs are low, and you can add design or Change PIN output at any stage of the design process, which can soon be listed.

The structure of CPLD:
CPLD is a programmable logical device of coarse-grained structure. It has abundant logical resources (high ratio of logical gate to register) and highly flexible routing resources. CPLD routes are connected together, while FPGA routes are separated. FPGA may be more flexible, but it includes many Jumpers, so the speed is slower than that of CPLD.
The CPLD is arranged as a group array (array of clusters) and connected by horizontal and vertical routing channels. These routing channels send or transmit signals to the pins of the device, and connect the logic groups in the CPLD.

The reason why CPLD is called coarse-grained is that the logical group is larger than the number of routes. The logic group of CPLD is much larger than the basic unit of FPGA, so FPGA is fine-grained.

Function Block of CPLD:
The most basic unit of CPLD is the macro unit. A macro unit contains a register (using up to 16 product items as its input) and other useful features.
Because each macro unit uses 16 product items, the designer can deploy a large number of combination logics without adding additional paths. This is why CPLD is considered a "logic-rich" type.

Macro units are arranged in the form of logical modules (LB). Each logic module consists of 16 macro units. The macro unit executes an and operation, and then an OR operation to implement the combination logic.

Each logical group has eight logical modules, and all logical groups are connected to the same programmable Interconnection Matrix.
Each group also contains two single-port logical group memory modules and one multi-port channel memory module. Each module of the former has 8 and 192b memory, and the latter contains 4 and 096b dedicated communication memory, which can be configured as a single port, multiple ports, or FIFO with dedicated control logic.

What are the benefits of CPLD?
Large I/O count
One of the benefits of CPLD is that it provides more I/O numbers on a given device density, sometimes even up to 70%.
Simple Time Series Model
CPLD is superior to other programmable structures in that it has a simple and predictable time series model. This simple time series model is mainly attributed to the coarse-grained characteristics of CPLD.
The CPLD can provide a wider equal state within a given period of time, regardless of the route. This capability is the key to successful design. It not only accelerates initial design, but also accelerates the design debugging process.

Advantages of coarse-grained CPLD structure:
CPLD is a coarse-grained structure, which means that the path of the incoming and outgoing devices goes through a few switches, and the corresponding delay is also small. Therefore, compared with the equivalent FPGA, CPLD can work at a higher frequency and have better performance.
Another advantage of CPLD is its fast software compilation, because its easy-to-route structure makes the layout design task easier to execute.

Advantages of fine-grained FPGA structure:
FPGA is a fine-grained structure, which means there is a fine-grained delay between each unit. If a small number of logics are closely arranged together, FPGA is fast. However, as the design density increases, the signal has to pass many switches, and the routing latency also increases rapidly, reducing the overall performance. The coarse-grained structure of CPLD can adapt well to the change of this design layout.

Flexible output pins
The coarse-grained structure and timing characteristics of CPLD are predictable, so the designer can still change the output pin at the later stage of the design process, while the timing remains unchanged.

Why does CPLD and FPGA require different logic design skills?
FPGA is a fine-grained device, and its basic unit and routing structure are smaller than those of CPLD. FPGA is of the "register-rich" type (that is, the ratio of its registers to the logic gate is high), while CPLD is the opposite. It is of the "logic-rich" type.

Many designers prefer CPLD because of its ease of use and high speed. CPLD is more suitable for logic-intensive applications, such as state machine and address decoder logic. FPGA is more suitable for register-Intensive design such as CPU and DSP.

New CPLD Encapsulation
CPLD has multiple density and encapsulation types, including single-chip self-guided solutions. The self-guided solution integrates flash memory and CPLD in a single encapsulation without external guiding units, which can reduce design complexity and save board space. Higher device density shared pin output within a given encapsulation size. This allows the designer to easily zoom in without having to change the pin output on the board.

Power Consumption of CPLD
Compared with FPGA with the same density, CPLD has lower standby power consumption.

Cpld fpga (standby current (when Vcc is 1.8V ))
50 K 300 μA 200mA
100 K 600 μA 200mA
200 K 25mA 300mA

CPLD is especially suitable for battery-powered applications that require low power consumption and low temperature, such as handheld devices.

Many designers are familiar with the traditional PLD and enjoy the inherent flexibility and ease of use of this structure. CPLD provides a good alternative for ASIC and FPGA designers to implement their design in a simpler and easier-to-use structure. The CPLD has reached the density of hundreds of thousands of doors and provides the high performance required for today's communication design. ASIC and FPGA are still needed for the design of more than 0.5 million doors, but CPLD is a cost-effective alternative for small design.

FPGA adopts a new concept such as Logic Cell Array (LCA), which includes Configurable Logic modules CLB (Programmable Logic Block) and Output Input module IOB (Input Output Block) and Interconnect. The basic features of FPGA include:
1) FPGA is used to design ASIC circuits. You can use the chips without generating chips. -- 2) FPGA can be used as a pilot Sample for other fully-customized or semi-customized ASIC circuits.
3) FPGA has a wide range of internal triggers and I/O