Differences between TTL and CMOS

What is TTL level, what is CMOS level, their difference
(1) TTL High Level 3.6 ~ 5 V, low 0 V ~ 2.4 V
CMOS-level VCC can reach 12 V
The output height of the CMOS circuit is about 0.9vcc, while that of the output low is about
0.1vcc.
The input that is not used by the CMOS circuit cannot be left blank, which may cause logical confusion.
The input end not used by the TTL circuit is suspended as a high level
In addition, the power supply voltage of the CMOS integrated circuit can be changed within a large range, so the requirement on the power supply is not as strict as that of the TTL integrated circuit.
They can be compatible with TTL levels.
(2) The TTL level is 5 V, and the CMOS level is generally 12 V.
Because the power supply voltage of the TTL circuit is 5 V, the power supply voltage of the CMOS circuit is generally 12 V.
The 5 V level cannot trigger the CMOS circuit, and the 12 V level will damage the TTL circuit, so it cannot be compatible with each other.
(3) TTL level standard
Output L: <0.8 V; H:> 2.4 v.
Input L: <1.2 V; H:> 2.0 V
The output low level of the TTL device must be less than 0.8 V, and the output high level must be greater than 2.4 v. If the input value is lower than 1.2v, it is regarded as 0. If the input value is higher than 2.0, it is regarded as 1.

CMOS level:
Output L: <0.1 * VCC; H:> 0.9 * VCC.
Input L: <0.3 * VCC; H:> 0.7 * VCC.

Generally, single-chip microcomputer, DSP, and FPGA can directly communicate with each other. under normal circumstances, the same voltage is acceptable, but it is best to check the values of devil, VIH, vol, and voh in the Technical Manual to see if they can be matched (Vol is smaller than devil, voh must be greater than VIH, which is in a connection ). Some are normal in general applications, but the parameters are not matching enough. In some cases, they may not be stable enough, or different batches of devices cannot run.

For example, the output of the 74LS device is connected to the 74hc device. In general, it works well, but the parameters do not match, and in some cases it cannot be run.

74LS and 54 series are TTL Circuits, while 74hc is CMOS circuits. If their serial numbers are the same, the logic functions are the same, but the electrical and dynamic performances are slightly different. For example, the logical high level of TTL is> 2.7 V, and the CMOS is> 3.6 V. If the first level of the CMOS circuit is TTL, there is a hidden risk of unreliable. Otherwise, there is no problem.

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TTL level:
Output High level> 2.4 V output low level <0.4 V
At room temperature, the output high level is generally 3.5 V, and the output low level is 0.2 V.
Minimum input high voltage and low level
Input high level> = 2.0 V input low level <= 0.8 V
Its noise margin is 0.4 V.
CMOS level:
1 logic level voltage is close to the power supply voltage, 0 logic level is close to 0 V. It also has a wide noise margin.

Level conversion circuit: the value of TTL and COMS is different (TTL 5 V = "CMOS 3. 3 V), so the level conversion is required for interconnection:
It is to use two resistors to divide the level, there is nothing advanced.

OC door, that is, open collector door circuit, it must be open resistance and power supply to switch level as high and low level. Otherwise, it is generally used only for switching large voltage and
High-current load, so it is also called the drive door circuit.

Comparison of TTL and COMS circuits:
1. the TTL circuit is the current controller, while the COMs circuit is the voltage controller.
2. the TTL circuit features high speed and short transmission delay (5-10ns), but high power consumption.
The speed of the COMs circuit is slow, and the transmission delay is long (25 -- 50ns), but the power consumption is low.
The power consumption of the COMs circuit is related to the pulse frequency of the input signal. The higher the frequency, the hotter the chip set.
3. Coms circuit locking effect:
Because the input current of the COMs circuit is too large, the internal current increases sharply. The current keeps increasing unless the power supply is cut off. This effect is the locking effect. When
When the lock effect is applied, the internal current of COMS can reach more than 40mA, And the chip is easily burned out.
Defense measures:
(1) Add a clamp circuit at the input and output ends so that the input and output cannot exceed the specified voltage.
(2) The power input of the chip is coupled with a decoupling circuit to prevent instantaneous high voltage at the VDD end.
(3) add a line resistance between the VDD and the external power supply, even if there is a large current, it will not let it in.
(4) when the system is powered by several power supplies separately, the switch should be enabled in the following order: when the power supply is enabled, the COMs circuit is first enabled, and then the input signal and the load of the Electricity
When the source is off, the power of the input signal and load is disabled first, and then the power of the COMs circuit is disabled.

4. Precautions for using the COMs Circuit
(1) When the COMs circuit is used as a voltage controller, it has a high total input resistance and is capable of capturing interference signals. Therefore, do not pin unused pins to be dropped.
Resistor or drop-down resistor to give it a constant level.
(2) When the input end is connected to a low internal signal source, a throttling resistor must be connected between the input end and the signal source so that the input current is limited to 1mA.
(3) When a long signal transmission line is connected, the COMs circuit is connected with a matching resistance.
(4) When the input end is connected to a large capacitor, the resistance should be indirectly protected at the input end and the capacitor. The resistance value is r = V0/1mA. v0 is the voltage on the external capacitor.
(5) If the input current of COMS exceeds 1mA, coms may be burned out.

5. Load Characteristics at the input end of the TTL door circuit (Handling of special cases with resistance at the input end ):
1. When suspended, the input end is connected to a high level. It can be seen that the input end is connected to an infinite resistance.
2. Input a low level after a 10 k resistor is connected at the input end of the door circuit. The input end shows a high level rather than a low level. Because the incoming load of the TTL Gate Circuit
We can see that only when the series resistance connected to the input end is less than 910 euros, the low-level signal it inputs can be identified by the door circuit. If the series resistance is large
The end is always high. Pay attention to this.
The COMS door circuit does not need to consider this.

6. the TTL circuit has an open-collector OC gate, and the mos tube also has an open-drain OD gate corresponding to the Collector. Its output is called an open-drain output.
The OC door has a leakage current output at the end, that is, the leakage current. Why is there a leakage current? That's because when the three-host pipe ends, its base current is approximately equal
0, but not really 0, the current through the transistor collector is not really 0, but about 0. This is the leakage current.
Open/leak output: the output of the OC gate is the open/leak output, and the output of the OD gate is also the open/leak output. It can absorb a large amount of current, but cannot output the current outward. Institute
In order to be able to input and output current, it must be used together with the power supply and the pull-up resistor.

The OD gate is generally used as an output buffer/driver, a level converter, and can meet the needs of absorbing large load current.
7. What is the Tumen pillar? What is the difference between it and the open-leakage Road?

In the TTL integrated circuit, the output with a pulling transistor is called the tengzhu output, but not the OC gate. Because TTL is a third-level off
Two three-level tubes are pushed and linked. So pushing and pulling is a totem.
General Graphic Output, high 400ua, low 8ma

TTL level (L level: less than or equal to 0.8 V; H level: greater than or equal to 2 V)
Coms level (L level: less than or equal to 0.3vcc; H level: greater than or equal to 0.7vcc)

The input ports not required by the CMOS device must be connected to the high or low level. This is because the CMOS device is a high-input impedance device and the ideal state is that there is no input current. if the unused input pins are left blank, it is easy to sense the interference signal, affecting the logical operation of the chip, and even accumulating static electricity to permanently penetrate the input end, resulting in chip failure.
In addition, only 4000 Series CMOS devices can work under 15 V power supply, 74hc, 74hct and so on can only work under 5 V power supply, now there are CMOS Logic Circuit chips working on 3 V and 2.5 V power supplies.

CMOS flat andTTL level:The CMOS level voltage ranges from 3 ~ 15 V. For example, when the 4000 Series is powered by 5 V, the output above 4.6 Is a high level, and the output below 0.05v is a low level. The input value must be greater than V, and the input value must be lower than v. For TTL chips, the power supply range is from 0 ~ 5 V, usually 5 V, such as 74 Series 5 V power supply, output above 2.7v is high level, output below V is low level, input above 2 V is high level, lower than 0.8v. Therefore, there is a problem of level conversion between the CMOS circuit and the TTL circuit, so that the two levels can match.

Concepts About logical level:
To understand the logic level, you must first understand the meanings of the following concepts:
1: Input high level (VIH): ensure that the input of the logic gate is the minimum input high level allowed by high voltage. When the input level is higher than VIH, it is considered that the input level is high.
2: input low level (devil): ensure that the input of the logic gate is the maximum input low level allowed by low power. When the input level is lower than devil, it is considered that the input level is low.
3: output high level (voh): ensure that the output of the logic gate is the minimum value of the output level of the high current. The output value of the logic gate must be greater than that of the voh.
4: output low level (VOL): ensure that the output of the logic gate is the maximum value of the output level at low power levels. The output value of the logic gate must be smaller than that of the vol at low power levels.
5: threshold level (VT): Each digital circuit chip has a threshold level, that is, the level when the circuit is barely able to flip. It is a voltage value between windows and VIH. For the CMOS circuit's threshold level, it is basically a 1/2 power supply voltage value, but it must ensure stable output, you must enter a high level> VIH and a low level <devil. If the input level is up or down the threshold ~ In the VIH area, the output of the circuit is unstable.
For general logic levels, the relationship between the above parameters is as follows:
Voh> VIH> VT> Devil> vol.
6: ioh: The logic gate outputs the load current (for pulling current) for high-power periods ).
7: fib: The logic gate output is the load current at low power usage (for irrigation current ).
8: iih: the input of the logic gate is the current of the high current (for the filling current ).
9: IIl: the input of the logic gate is the current at low power consumption (for pulling current ).
The gate circuit output pole is directly output as the output end without load resistance in the Integration Unit. This form of door is called an open door. Open-source TTL, CMOS, and ECL are called Open-collector (OC), open-drain (OD), and open-source (OE) respectively ), when used, check whether the Pulling Resistance (OC, OD gate) or drop-down resistance (OE gate) is connected and whether the resistance is suitable. For open collector (OC) doors, the uplink resistance RL must meet the following conditions:
(1): RL <(VCC-voh)/(n * ioh + M * iih)
(2): RL> (VCC-Vol)/(OLS + M * IIl)
N: number of open doors and wires; M: Number of input ports driven.
: Common logic levels
· Logic level: TTL, CMOS, lvttl, ECL, PECL, GTL, RS232, rs422, and LVDS.
· The logical levels of TTL and CMOS can be divided into four types by typical voltages: 5 V series (5 v ttl and 5 v cmos), 3.3v series, 2.5v series, and 1.8v series.
· 5 v ttl and 5 v cmos logical levels are common logical levels.
· 3. logical levels of 3 V and below are called low-voltage logical levels, which are commonly used as lvttl levels.
· The logical levels of low voltage include 2.5v and 1.8v.
· ECL/PECL and LVDS are differential input and output.
· RS-422/485 and RS-232 are serial port interface standard, RS-422/485 is differential input output, RS-232 is single-ended input output.

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1. CMOS is composed of FET, and TTL is composed of Bipolar Transistor
2. The logical level range of COMS is relatively large (5 ~ 15 V), TTL can only work under 5 V
3. The difference between the high and low levels of CMOS is relatively large, the anti-interference is strong, the TTL is slightly different, and the anti-interference capability is poor
4. Low CMOS power consumption and high TTL power consumption (1 ~ 5mA/Door)
5. The operating frequency of CMOS is slightly lower than that of TTL, but the high-speed CMOS speed is similar to that of TTL.

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The OC gate, also known as open collector (open drain) and non-gate circuit, open collector (open drain ). Why is OC introduced?

In actual use, sometimes two or more non-door output ends need to be connected to the same wire, these and non-door data (status level) with the same wire transport out. Therefore, a new and non-gate circuit-OC gate is required to implement "line and logic ".

The OC gate is mainly used in three aspects:
1,

Implement and non-logic, use for level conversion, use for drive. Because the collector of the output tube of the OC gate circuit is suspended, an external pull-up resistor RP must be used to power the VCC. The OC door uses a pull-up resistor to output a high level. In addition, in order to increase the drive capability of the output pin, the principle of selecting the pull-up resistor resistance is as follows, it should be large enough to reduce power consumption and chip current filling capacity, and small enough to ensure sufficient driving current.
2,
Line and logic, that is, the two output ends (including more than two) can be directly connected to implement the "and" logic function. In practical applications such as bus transmission, the output ends of Multiple doors need to be connected in parallel. Generally, the output ends of TTL doors cannot be directly connected, otherwise, a large short-circuit current (fill current) is formed between the output tubes of these doors due to low impedance, and the device is burned out. On the hardware, it can be implemented by oC or tri-state gate (ST gate. When the OC door is used to achieve the line and the output port, a pulling resistance should be added at the same time.
3,
The three-state gate (ST gate) is mainly used for multiple gate outputs to share the data bus. To prevent multiple gate outputs from occupying the data bus at the same time, the enabling signals of these gates (en) only one valid level (such as high level) is allowed, because the output of the three-state gate is a low-resistance output of the pull type, and the pulling (load) resistance is not required, therefore, the switching speed is faster than that of the OC gate, and the three-state gate is often used as the output buffer.

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A) what are setup and holdup time?
The setup time refers to the time when the trigger's clock signal remains unchanged before the rising edge of the trigger. If the time is not enough, the data cannot be pushed into the trigger on the rising edge of the trigger; hold time refers to the time when the rising edge of the trigger's clock signal arrives, and the data remains unchanged. If the hold time is not enough, the data cannot be pushed into the trigger.

B) What is competition and adventure? How to judge? How to eliminate it?
The signal has a certain delay when the FPGA device is connected to the logical unit. The delay is related to the length of the line and the number of logical units. It is also affected by the manufacturing process, operating voltage, temperature, and other conditions of the device. The signal's high/low level conversion also requires a certain amount of transition time. Due to these two factors, when the level value of a multi-channel signal changes, the output of the combination logic is sequential at the moment of signal changes, but not at the same time, some Incorrect peak signals are often called "burrs ". If a combined Logical Circuit contains a glitch, it indicates that the circuit has an adventure ". The use of D triggers, Gray Code counters, synchronization circuits and other excellent design solutions can be eliminated.

C) How can I draw a logic circuit that uses the D trigger to achieve 2x division of data?
That is, the output end of the D trigger is added to the d end.

D) What is "line and" Logic? What are the specific requirements on hardware features for implementing it?
Several oc-gate structures and Non-gate outputs are connected in parallel. When each oc-gate output is high, the total output is high. This connection mode is called line-and-non-gate output.

E) What is the synchronization logic and asynchronous logic?
In the whole design, only one global clock becomes the synchronization logic.
The logic of the Multi-Clock System is designed as Asynchronous logic.

F) draw out the typical input device and microcomputer interface logic (data interface, control interface, recorder/buffer) in the microcomputer interface circuit ).
Is it a structure chart?

G) Do you know the common logic levels? Can TTL and COMS levels be directly interconnected?
TTL, CMOS, cannot be connected directly
LVDS: LVDS (low voltage differential signal) is a low-voltage differential signal. The LVDS interface, also known as the rs644 bus interface, is a data transmission and interface technology that emerged in 1990s.
ECL :( emittercoupled logic) is a typical input/output interface circuit with an output structure.
The standard definition of the standard definition. Its input and output are well matched, which reduces peripheral devices and is suitable for working in higher frequencies.