Hardware Description Language (HDL)
Summary
With the development of EDA technology, designing PLD/FPGA using hardware languages has become a trend. Currently, the most important hardware description language is
VHDL.
VHDLThe development of explicit presentation and fine-grained structured erilog HDL is a hardware description language developed on the basis of the C language, with a relatively free syntax.
VHDLCompared with those of the two,
VHDLThe writing rules are more complex than those of the Tilde. However, the free syntax of the Tilde language is also easy for a few beginners to make mistakes. Many foreign electronic majors will be taught at the undergraduate level
VHDLHe is a graduate student and a professor at the master's level. From the domestic perspective,
VHDLThere are a lot of reference books, which are easy to find information, while there are relatively few reference books for the Tilde, which brings some difficulties to learning the Tilde. From the perspective of the development of EDA technology, hardware C language compilation software for CPLD/FPGA design has emerged. Although it is still immature and rarely used, it may become a secondary
VHDLAnd then, design another method of large-scale CPLD/FPGA.
SelectVHDLOr is it using Tilde?
This is the most common problem for beginners. In fact, the two languages are not very different, and their descriptive capabilities are similar. After learning one language, you can quickly learn another language through short-term learning. The language you choose depends on the usage habits of the people around you to facilitate future study and communication. Of course, if you are an integrated circuit (ASIC) designer, you must first master the Integrated Circuit (ASIC), because in the IC design field, more than 90% of the companies use the Integrated Circuit (ASIC) for IC design. For PLD/FPGA designers, the two languages are free to choose.
Tips for learning HDL
1. Understand the comprehensive problems of HDL:
HDL has two purposes: System Simulation and hardware implementation. If the program is only used for simulation, almost all syntax and programming methods can be used. However, if our program is used for hardware implementation (for example, FPGA design), then we must ensure that the program is "Comprehensive" (the program functions can be implemented using hardware circuits ). Non-Integrated HDL statements are ignored or reported when integrated software is used. We should keep in mind that "All HDL descriptions can be used for simulation, but not all HDL descriptions can be implemented using hardware ."
2. Use the hardware circuit design idea to compile the HDL:
The key to learning HDL well is to fully understand the relationship between HDL statements and hardware circuits. Writing HDL is to describe a circuit. After writing a program, we should have a general understanding of the generated circuit, rather than writing a hardware description language using a pure software design idea. To achieve this, we need to practice more, think more, and summarize more.
3. More advanced syntax skills
30% of basic HDL statements can complete more than 95% of circuit design. Many uncommon statements cannot be supported by all integrated software. When the program is transplanted or replaced with the software platform, it is prone to compatibility issues and is not conducive to reading and modifying others. It is recommended that you carefully study common statements to understand the hardware meanings of these statements, which is more useful than mastering several New syntaxes.
Relationship between HDL and schematic Input Method
The relationship between HDL and traditional schematic input methods is like the relationship between high-level languages and assembly languages. High-portability and ease-of-use of HDL, but its efficiency is not as good as that of schematic diagram. The input of schematic diagram is controllable, efficient, and intuitive. However, it is cumbersome and portable to design large-scale CPLD/FPGA. In the real PLD/FPGA design, it is usually recommended to use the schematic diagram and the combination of HDL to design, suitable for the use of the schematic diagram, where the use of HDL is suitable for use, there are no mandatory rules. In the shortest time, we can use our most familiar tools to design efficient, stable, and compliant circuits.
HDL Development Process
Use
VHDLThe complete process for developing PLD/FPGA in/veriloghd is as follows:
1. text editing: You can use any text editor or a dedicated HDL editing environment. Usually
VHDLThe file is saved as a. vhd file, and the pixel file is saved as A. V file.
2. function simulation: transfers the file to the HDL simulation software for functional simulation, and checks whether the logic function is correct (also called the pre-simulation, you can skip this step for a simple design, only after the wiring is completed, timing simulation)
3. logical synthesis: the source file is integrated into the logical synthesis software, that is, the language is integrated into the simplest Boolean expression and the signal connection relationship. The logical synthesis software generates the. EDF (edif) EDA industry standard file.
4. layout and wiring: transfer the. EDF file to the software provided by the PLD manufacturer for cabling, that is, place the designed logic in the PLD/FPGA.
5. Timing simulation: Use the precise parameters obtained in the layout and wiring to verify the timing of the circuit with simulation software. (Also called post-simulation)
6. program download: After confirming that the simulation is correct, download the file to the chip.
Generally, the above processes can be completed in development tools provided by PLD/FPGA Manufacturers (such as maxpluⅱ, foundation, ISE), but many integrated PLD development software only supports
VHDLThe subset of/Tilde may cause a few syntaxes to be unable to be compiled. If you use dedicated HDL tools for separate execution, the effect will be better. Otherwise, there will be no reason for so many companies that sell specialized HDL development tools.
