Digital integrated circuit design -16-about Axi protocol

Introduction

The AXI protocol is probably a protocol that we often encounter in our usual circuit design, and it's a good deal, and we'll be familiar with this section.

At first glance, the AXI protocol signals are numerous, dazzling and easy to Fameng. But in fact its basic idea is very simple. Just grasp the following points:

1,valid/ready protocol
The Axi protocol is a typical bus protocol based on the Valid/ready protocol.
The advantage of the Valid/ready protocol is that the relative independence of master and slave is better.
For a single transmission, the initiator of master does not have to check if the salve is ready, it can put the transmission content on the bus;
Also for the receiver's slave, as long as the new data can be received, you can put the ready signal on the bus, do not wait for master to initiate the transmission.
The Valid/ready protocol can effectively decouple both master and slave, and can effectively reduce the overhead of the ' transfer handshake '.
This differs from the general ' Request/ack ' serial protocol. For example, Ahb,apb,wishbone and other on-chip bus protocol.
Because the Valid/ready protocol has the above advantages, it is widely used in the actual digital design, not only for on-chip bus, the data exchange between each module, but also the Valid/ready protocol can be used.
With regard to the Valid/ready agreement, there is a paper that can be consulted:
Eecs150:interfaces: "FIFO" (a.k.a. Ready/valid) UC Berkeley College of Engineering
Department of electrical Engineering and computer science


2, the chaotic Axi protocol is the protocol that supports the chaotic transmission, that is, Master has initiated two transmissions, and the order of slave and master initiation sequence can be different. How does Axi carry out the chaotic sequence of transmissions? There are two points that are very important, namely ID and parallelism. Regarding the ID, we need to get enough attention, in the AXI protocol spec inside the signal list put him in the first, visible this ID of importance. It can be said that without the ID of this signal, you can not achieve chaos sequence. In addition, in the actual application, the ID can also assume in addition to the ' disorderly order ' this important task, other important tasks. For example, you can put information from different CPUs in the ID and so on ... Of course, you can put all the additional information on the user signal to assume, but consider compatibility, put in the ID will be better.


3, parallel on parallel, ' channel separation ' is the potential basis for parallel performance.

Channel separation, which is easy to understand, means that Axi will not only separate the read and write operations, but also divide the information used by the read and write operations into different channels.

The write operation is divided into 3 channels, and the read operation is divided into 2 operations.

Here, there is a point to remind: from a philosophical point of view, read operations and write operations are symmetrical, is equivalent, one to write a read, a go back, not read where to write, did not write why read, as if Taiji figure inside a black and white, how harmonious and symmetrical. Why the Axi protocol write operation has 3 channels, read operation but only 2 channels, this is blatant to read operation discrimination Ah! What is this for?

I think it can be explained from two angles?

First, it may be related to consistency. RESP channel of an important responsibility is to remove the consistency (WAW,WAR,RAW), imagine if the read operation of the Rdata and Rresp split into two separate channels, and what wonderful scenario will appear in the back of the write operation has not been read operation returned data can be lifted consistency?! That is, even if the need to read the operation of the strong requirements, it is also divided into 3 separate channels, there will be no rdata and rresp asynchronous situation, since the split out of the two channels are synchronous, then there is no need to split.

Second, it may be related to philosophy, read and write seemingly equal, actually there is inequality, such as waw rely on, but no RAR dependency, the world is not equal, you read operation why must and write operation everywhere equality, you and write operations apart is already thought highly you, really uncomfortable words, read and write together, It becomes a low-speed, high-coupling, serial, no-mess protocol, such as AHB,APB or wishbone.

The same serial, sub-parallel, is the division, is slow, the minute is fast, choose it yourself.

Of course, it is not that ' hop ' is useless, ' hop ' will greatly reduce the number of signals.

is the pursuit of transmission speed or the pursuit of a small number of signal lines, choose it yourself.

4, relying on the completion of parallel, and then rely on. Parallelism and dependency are also a pair of contradictions.

From a large point of view, for read/write, most of the time can be considered parallel, but the read-write address conflicts, there is a reading/writing and dependency.

From a small point of view, pure for the write operation, AW, W, b three channels from the formal view is independent of the parallel, but three channels in the logic of a certain dependence.

For example, Master's W-channel write-data allows the write address of the AW channel to be sent first to the bus? Allowed, not allowed, can be.

If not, can the ID signal of the W channel be removed? The answer is can be removed, as long as the wdata sent to the bus after the order and the AW channel data sent to the bus in the same order, and this guarantee is easy to do.

Does the valid on the slave b channel allow the valid to be sent out earlier than the AW and W channels?

Obviously is not allowed, imagine, slave has not received the data to tell master you have received, not error is strange.

Of course, nothing is absolute, and if you add some constraints to master and slave on the basis of the Axi standard protocol, Slave's bvalid is also allowed to be sent out earlier than the AW and W two channel valid, which is the wonderful work of writing for the arm A9 ' Early resp '.

5,barrier Transmission In fact, the standard AXI4 inside does not have barrier transmission, within the ACE Protocol, ACE is a consistent bus protocol for multicore systems.

But sometimes, the need for barrier transmission in a single-core system is also urgent (such as when the CPU needs to synchronize with the DMA device), but what if there is no need to fully support the ACE protocol?

You can simply introduce the ' bar ' signal in the ACE.

For barrier. You need to figure out two points:

First, what is the operation before barrier, what is the operation after barrier;

The actions before barrier refer to the operations that were issued before the barrier signal on the respective channel (AW/AR) was valid. The operations after barrier refer to the operations that are issued after RESP (BRESP/RRESP) on the respective channel is returned. It should be noted here that there are some operations in the ' barrier signal after the RESP signal back ' sent, they do not belong to barrier before the operation, is not part of the operation after barrier, belong to what? They are called ' outstanding operations '.

Second, what is the difference between memory barrier and synchronization barrier.

With regard to memory barrier and synchronization barrier, my understanding is:

The requirement of memory barrier is to barrier the RESP signal of this command back to the line (regardless of the outstanding), to ensure that the command behind it can see the result of the command issued earlier.
The requirements of system barrier are to barrier the RESP signal of this command back to the line, to ensure that the command before it is completed completely, that is, not only the cache down.
Two possible usage scenarios:
Memory Barrier:
A physical CPU (which can be multiple logical cores) runs on two threads, one thread (a) updates an array, and after the update is completed it needs to tell the other thread (b) that the thread B reads the value of the array after the update.
For this scenario, after thread a updates the array, sending a memory barrier command guarantees that thread B can read the updated value.
System Barrier:
A physical CPU (which can be multiple logical cores) running on a thread, this thread updates an array and needs to tell Vpu,vpu the value of the array after the update is finished.
For this scenario, the thread above the CPU updates the array, sending a system barrier command to ensure that Vpu reads the updated value. If only a memory barrier command is sent, the most recent value may be cached in the L1/L2 cache, causing Vpu to read the old value.

6, summary in short, Axi is a very good protocol, but in the use of the process to have their own ideas, you can do some appropriate work.

After all, the agreement was set by arm, but the circuit was designed by you. The shoes fit the foot, only you know the most clearly.

7, appendix AXI4 Vs ACE

Digital integrated circuit design -16-about Axi protocol