Disable the use of the divider clock, counter clock

Watch Yu Qiao The video of the teacher, referring to the above questions, carefully search under the research:

It is forbidden to use the counter-divided signal as the clock of other modules, but to change the clock to enable the way. Otherwise, the way the clock is flying is extremely detrimental to the reliability of the design and greatly increases the complexity of the static timing analysis. Clock enable circuit is an important basic circuit of synchronous design, in many designs, although the internal different module processing speed is different, but because these clocks are homologous, can convert them to a single clock circuit processing. In the design of FPGA, the skew of frequency division clock and source clock are not easy to control, it is difficult to guarantee the phase-divider clock and source clock. It is therefore recommended to use a clock-enabled method.

Clock generation: Two reading Master program, two methods of processing. The first processing method is in the frequency Division mode , because the clock duty ratio after the division is 50%, in the use of this frequency-divider signal for the clock to drive, through the logic of the signal to determine the pre-and post-state signals, whether the clock enable signal is rising edge , Then run the program module under the logical rising edge. At that time to see such a deal, it is entirely considered simple problem complex words, direct use of the clock driver module after the crossover can be directly on the rising edge of the process.

The second method of processing is to use a counter to generate a frequency divider clock , only in a certain number of values to the clock enable, you can keep the clock enable high level only to maintain a CLK cycle, so that the program can be run on the clock to rise on the edge. Again, when the clock enables the driver to be able to do so, it is not known that there is such a design idea, which creates some confusion when reading the program module directly.

Turn from:

Http://forum.eepw.com.cn/thread/236499/1

Disable the use of the divider clock, counter clock