Video Input decoding module
Video input decoding module consists of 4 TVP5150 video decoder and peripheral circuit, the main function is to send each CCD camera input standard PAL TV analog signal to the video decoder, to complete the video image clamp and anti-aliasing filtering pretreatment, analog digital turn and brightness/chroma, Level/ Vertical synchronization and other signal separation, the realization of analog video signal conversion to digital parallel signal bt.656 stream format, TVP5150 can be baseband analog NTSC, PAL and SECAM video signal conversion to digital component video signal, the normal operation of power consumption is only 115mW, the price is lower than the same series of TI products and has the industry's smallest 32-pin thin square flat package (TQFP). The TVP5151 supports up to 2 composite terminals or 1 S-terminal inputs, outputs itu-rbt.656, and supports Macrovision copy protection and advanced VBI functionality.
DM642 Video Port 0, 1 part (vp0/a, vp1/a) and video Port 2 (vp2/a, vp2/b) respectively, 1 TVP5150, video capture data format Yuv4:2:2, the resolution is CIF (352x288) size, The video input decoding module interface circuit principle functional block diagram is shown in Figure 2. The system connects the I²c bus interface of the 2 circuits to the SCL and SDA respectively, TVP5150 the video output port yout[0-7] and vpod[9-2 of the DM642 vport port), TVP5150 the system clock SCLK and DM642 The VPOCLK0 of the Vport mouth is connected. Due to the use of the ITU-R bt.656 stream format, synchronization signals such as horizontal synchronization, vertical synchronization, and field synchronization are embedded in the video data stream, and take into account the 3 vp0ctl[0-2] control pins reserved by each Vport port to receive the sync signal DM642 Can only meet the requirements of the video synchronization signal, so in the design process to omit the synchronization signal line connection.
TVP5150 Although the scaling function is not supported, but can intercept part of the screen and then pass to DM642 for subsequent compression processing, the specific operation is to select the corresponding register in the video stream of the beginning and end of the line, control the image of the longitudinal length, Select the start and end positions of a single line and take advantage of the image's avid features to control the horizontal width of the image.
DM642 access to the TVP5150 internal register is implemented via the I²C bus, which requires an address 0x101110x1 from the device TVP5150 during the TVP5150 response, where x represents 0 or 1 and can be configured when the system is power-up. TVP5150 at power-up depending on the potential of the yout[7], x represents 0, or 1. In this way, the TVP5150 as the slave device has only 2 addresses: 0x10111001 and 0x10111011. DM642 to communicate with 4 TVP5150, all-in-one bus is not enough, it is necessary to use the Gpio interface to simulate the I²C bus timing, configure another two TVP5150.
The digital video data of the acquisition output is fed into the 5120 bytes size buffer of the DM642 Vport port, and the TVP5150 channel automatically sends data to the EDMA DM642 Port buffer unit under the control of the local clock, and the DMA interrupt is generated when the data is collected. And in the DMA interrupt service program according to the actual need to complete the corresponding video processing, after the real-time encoding compressed video data stored in the external SDRAM, the hardware circuit needs to provide TVP5150 required 14.31818 m Hz clock frequency, The DM642 can be set via the I²c bus for TVP5150 parameters.
Audio Input Acquisition Module
The audio input acquisition module consists of 2 pcm1801u audio acquisition circuit and its peripheral circuit, the main function is to sample the analog audio signal collected by pickup, then convert it to digital audio data format which can be processed by DSP, The pcm1801u is a two-channel 16-bit audio modulo/number (A/D converter with a 5 v operating voltage, including 1 single-ended-differential analog front ends, a 5-step sigma Modulator (64 times-fold repeat sampling), and 1 internal high-pass digital averaging filters.
The remainder of the DM642 video port 0, 1 (vp0/b, vp1/b) is configured as mcasp, with 1 pcm1801u connections for audio input acquisition functions. Using Pcm1801u's left and right 2 16-bit audio channels to obtain the digitized data of 4 channel audio channels, the data format of audio acquisition is per mono channel, 44.1K Hz sampling rate, each sampled data is quantified with 8 bits, the digital audio data of the acquisition output is passed mcasp to the input buffer unit of DSP. When the buffer used to hold audio sampling data is full, the DMA interrupt is generated, and the audio data is processed according to the actual setting in the DMA Interrupt service program, and the audio data is stored in the external SDRAM via the real-time encoded compression, and the DSP encodes the audio acquisition circuit through the I²C bus to control the sampling rate. , audio Source, volume and other specific parameters, hardware circuit needs to provide audio acquisition circuit required work clock, I use the clock is 11.2896M Hz, audio input Acquisition module interface circuit principle functional block diagram as shown in Figure 3.
Core DM642 DSP Module
The core DM642 DSP module consists of 1 tms320dm642 digital media processor and its peripheral circuit, mainly to the internal input cache digital audio, video data stream processing and compression, video image signal compression is generally lossy compression, while the system must meet the real-time encoding, So the use of fixed-point DSP can better meet the entire compression system to the accuracy and speed requirements, the board design of the DM642 is specifically for the field of image video design, has a complete off-chip interface, can be more convenient to expand the external memory peripherals.
C64XX Series DSPs have a large number of byte-settable address spaces, and program code and data can be stored anywhere in the unified standard 32-bit address space. The memory map shown in table 1 shows the address space of the DM642 processor used by the Board, and, by default, the internal registers are stored from the 0x00000000 address space. Part of the memory is remapped by software to the L2 cache.
DM642 's EMIF has 4 independent address-setting zones, called circuit Enable space (ce0-3), which combine to form a 64-bit long external memory port, dividing the address space into 4 circuit enable zones, allowing for 8-bit, 16-bit, 32-bit, and 64-bit synchronous or unsynchronized access to the address space. At present, the board uses the circuit to enable the zone CE0, and assigns it to the 64-bit SDRAM bus. Ce1-3 's circuit enable zone is temporarily unused and can be used as a future extension for distribution to 8-bit flash, UART, FPGA, and sub-board interfaces.
The board is connected to the 64-bit SDRAM bus in the CE0 space and is connected to 2 hy57v283220tp-6 to form the SDRAM. Each hi57v283220tp-6 is the SDRAM of the 32-bit data bus, wherein the high 32 bits are stored in 1 SDRAM, the low 32 bits are stored in another 1 SDRAM to meet the requirements of the DM642 64-bit data bus, the 32MB SDRAM space is used to store programs, Data and video information. The bus is controlled by an external PLL drive device and operates at the optimal state of 133M Hz. The refresh of SDRAM is automatically controlled by DM642.
DM642 can configure the original value of the EMIF clock. The default value is selected for the Eclkin pin of the board. The EMIF clock frequency can also be controlled by the frequency divider CPU clock. The operation of the ECLKNSEL0 and ECLKINSEL1 pins is set during initialization, and they share the EMIF address space with the EA19 pin and the EA20 pin. PCI Bus driver control module
PCI bus driver control module consists of 1 sn74cbt16233 PCI bus bridge circuit and its external circuit, the signal in this module can be divided into system signal, address data multiplexing signal and interface control signal, etc., the system signal includes CLK and RST, provides clock and reset for the system, For the address data multiplexing signal, during the bus transmission operation cycle, 1 PCI bus cycles consist of 1 address segments and 1 or more data segments immediately followed, where ad[0-31] is the address data multiplexing bus that provides the address and data signal for the PCI interface circuit, multiplexed pin pcbe[0-3] Provides a bus command signal and a byte allow signal for the PCI interface circuit. Interface control signals are mainly composed of Frame,trdy, Irdy and Devsel signals, wherein frame signal is the bus cycle constitutes a signal, driven by the main device of the current bus, indicating the beginning and continuation of 1 bus cycles; Trdy is the target device ready signal, write operation, Trdy effectively indicates that the device is ready to receive data, while in the read operation, Trdy effective indicates that ad[0-31] has valid data, Irdy indicates that the drive device is ready for data, Devsel for the device to select the signal, when it is valid, The main device that drives it has decoded its address as the target device of the current operation, when the signal as input signal, the Devsel is used to indicate that the target device on the bus is selected, the other PCI bus required but the system does not use the signal can be replaced by high impedance state, The functional block diagram of the interface circuit of the PCI bus driver control module is shown in Figure 4.
This board is connected to the PCI bus using the 1 master/Slave PCI interfaces integrated in the DM642 DSP chip, which supports the PCI 2.2 specification and enables the interconnection of the DSP to the PCI host via the PCI bus. The host can access the entire on-chip RAM and the external memory through the DM642 PCI interface, the DSP EMIF transmits the data to the DSP memory through the EDMA, EMIF supports the synchronous FIFO, in order to enable the PCI bus to read the video compressed data stream in real time, and transmit to the host in a timely manner, The system uses the interrupt mechanism, when the FIFO is full, the DSP generates an interrupt signal, notifies the PCI interface module to start the DMA, the data to be transmitted by the FIFO by the DSP using DMA transmission mode between the computer and the Board to achieve high-speed video compression stream transmission, Provides high-speed transport interfaces without affecting other DMA operations.
Power Management module
This card through the PCI slot power supply, the choice of AMS1085 and AMS1086 to provide the board normal operation of the regulated power supply, AMS1085, AMS1086 are 3-terminal adjustable voltage regulator ICS, AMS1085 output Current is 3 A, output voltage is 1.5v/3.3v/5.0v,ams1086 output current is 1.5A, output voltage is 1.5v/1.8v/3.3v/5.0v. They are relatively easy to use and have protection measures such as short-circuit current protection and overtemperature protection, with high precision output voltages and operating stability. At design time, the internal v input power supply is rectified to +1.4v, +1.8v and + 3.3v, wherein the +1.4v voltage is provided to the DSP processor, and the +1.8v voltage provides the tvp5150,+3.3v voltage to the I/O in the DSP and other circuitry on the board. The Schottky diode should be connected between the 3.3V and 1.4V power supplies, guaranteeing simultaneous power to the DM642 core and the external port.
