DM9000 Drive on the MINI2440 transplant Learning notes

I want to know about the transplant modification principle of DM9000, so I analyzed the sequence diagram and PIN connection.

First, take a look at DM9000 pins and MINI2440 pin connections.

DM9000 MINI2440 Function Description
SD0 DATA0 Data Signal
| |
SD15 DATA15 Data Signal
is the CMD ADDR2 recognized as an address or a data
INT EINT7 Interrupt
ior# NOE Read command to enable
iow# nwe Write orders to enable
Aen nGCS4 tablet selection enabling

You can see that there are 16 data lines, 1 address lines, and the only address line is used to determine whether the data line transmits addresses or data, so the 16 data lines are data and address multiplexing

In the case of the BANK4, the 0x2000 0000–0x27ff FFFF the address of this range will activate the chip-selectable signaling nGCS4

In the kernel provided by MINI2440, DM9000 's address IO address is 0x2000 0000, and data io is 0x2000 0004
While writing data to address IO does not activate ADDR2, so the data sent to DM9000 is the address, and the ADDR2 is activated when the data is written to Io, so the data sent to DM9000 is data

Now look at the DM9000 and s3c2440 timing signals.

DM9000 Write timing Io16,io32 These two pins are not connected in MINI2440, so do not look at the timing of these two pins
What about the following:
There is the write command so that after the end to the next write command so that can require a minimum of 84ns interval, for T6
Then the s3c2440 writes the timing, because the DM9000 is connected to the BANK4, and the bank writes the time sequence as follows

Because the DM9000 on the MINI2440 only need the slice to be able, writes the command to enable and the data signal, therefore we do not look at the addr and the nbe signal, then does the collation as follows? How much are these values? ~ Look at BANKCON4

The value here is a clock cycle, and Bankcon is connected to the memory controller (refer to table 1-4 of the s3c2440a data manual), while memory controller uses the HCLK Bus clock signal ( Reference s3c2440a Data manual Figure 7-1, thanks to Kasim, according to s3c2440 Manual, Hclk is by the FCLK division, the specific frequency is different than the setting of each board, so here to set the frequency of their own according to the board set to analyze, Assuming the frequency is 400MHz, then fclk,hclk,pclk for 1:2:4, then HCLK is 200MHz, then? Each clock cycle is 5ns

Start with the DM9000 sequence diagram to compare and compute
TCOs corresponds to T1, it should be at least 5ns, namely 1 clock
TACC corresponding T2, it should be at least 22ns, then we have to choose at least 6 clock, that is, 30ns
Toch corresponds to T5, there is no setting, but according to the literal meaning, I think Tcoh is Toch,toch should be at least 5ns, that is, 1 clock
Tcah corresponds to T4, because there have been toch before, then this can be set to 0ns, which is 0 clock

In s3c2440, a write command makes it possible to end the next write command so that the time interval that can begin is Toch + Tcah + TACP + tacs + TCOs
TACs is the initial interval of the signal after the address signal, we first set it to 0ns, which is 0 clock

Toch + Tcah + TACP + tacs + TCOs should > 84
5 + 0 + TACP + 0 + 5 > 84
TACP > 74
But the maximum value of TACP is 6 clock, that is, 30ns, less 44ns, about 9 clock
As long as we modify the Toch Tcah TACs and TCOs, although we give the minimum value, but in order to signal stability, we can relax its range,
Set the TCOs and Toch to 4 clock
Set the TACs and Tcah to 2 clock
Such total time for (4 + 2 + 6 + 2 +4) *5 = 90ns

The last DM9000 1 cycles can only handle 1 data, so the PMC should be normal (1data)

Write the Time-series analysis, now read the timing

DM9000 's reading sequence is as follows: Read the command so that after the end to the next read command so that can require a minimum of 80ns intervals, for the T6
Then there is the s3c2440 reading sequence, which is as follows

Sorted as follows:

TCOs corresponds to T1, it should be at least 5ns, that is, 1 clock, which is set to the same as the write operation of the 4 clock
TACC corresponds to T2, it should be at least 22ns, this is set to the same as the write operation of the 6 clock
Toch corresponds to T5, it should be at least 5ns, that is, 1 clock, which is set to the same as the write operation of the 4 clock

Other time intervals are set to the same as the write operation
Tcah for 2 clock
TACP for 6 clock
TACs for 2 clock
PMC is normal (1data)
Then look at the time interval 80ns that satisfies the read command to enable the next read command to be completed

or Toch + Tcah + TACP + tacs + TCOs
(4 + 1 + 6 + 1 + 4) * 5 = * 5 = 90ns, able to meet the conditions

What about it? BANKCON4 is set as follows
TACS = 2 Clock = 10
TCOs = 4 Clock = 11
TACC = 6 Clock = 100
Tcoh = 4 Clock = 11
Tcah = 2 Clock = 10
TACP = 6 Clock = 11
PMC = Normal (1data) = 00

which is 0X5CEC.

To see Bwscon, this register is responsible for configuring the bank's bandwidth and wait status
We're taking nGCS4, what about the St4,ws4 and DW4 fields?
DW4 is described as BANK4 bandwidth, DM9000 received 16 address lines, then the bandwidth is 16, here choose 01
WS4 's description is whether the wait state is used for BANK4, DM9000 does not pick up the waiting pins, so you can ignore this field
ST4 is described as whether to use ub/lb for BANK4 (write high/low byte enable), DM9000 not connect nwbe[3:0] These 4 pins, so also regardless of this field

Now look at the friendly Linux DM9000 driver for adaptation s3c2440 what modifications

#if defined (config_arch_s3c2410) #include <mach/regs-mem.h> #endif #if defined (config_arch_s3c2410) Gets the address of the bandwidth and wait state control register unsigned int oldval_bwscon = * (volatile unsigned int *) S3c2410_bwscon; Get the address of the 4th Bank's control register. unsigned int oldval_bankcon4 = * (volatile unsigned int *) S3c2410_bankcon4; #endif #if defined (config_arch_s3c2410) First clear the DW4 on the Bwscon to 0. Then set the bandwidth to 16 bits Enable BANK4 wait Status Enable BANK4 SRAM to write high and low byte enable * ((volatile unsigned int *) s3c2410_bwscon) = (Oldval_bwscon & ~ (3<<16)) | S3c2410_bwscon_dw4_16 | S3c2410_bwscon_ws4 | S3c2410_bwscon_st4; Set Pmc-page mode configuration-1 data Tacp-page mode access cycle @ Page mode-6 clocks Tcah-address hold time after nGCSn-4 clocks Tcoh-chip selection hold time after nOE-1 clock Tacc-access cycle-14 Clocks Tcos-chip selection set-up time before nOE-4 clocks Tacs-address set-up time before nGCSn-0 clock * ((volatile unsigned int *) s3c2410_bankcon4) = 0x1f7c; #endif #if defined (config_arch_s3c2410) PRINTK ("Now use the default MAC address:08:90:90:90:90:90/n"); MAC_SRC = "Friendly-arm"; Ndev->dev_addr[0] = 0x08; NDEV-&GT;DEV_ADDR[1] = 0x90; NDEV-&GT;DEV_ADDR[2] = 0x90; NDEV-&GT;DEV_ADDR[3] = 0x90; NDEV-&GT;DEV_ADDR[4] = 0x90; NDEV-&GT;DEV_ADDR[5] = 0x90; #else #if defined (config_arch_s3c2410) * (volatile unsigned int *) S3c2410_bwscon = Oldval_bwscon; * (volatile unsigned int *) S3c2410_bankcon4 = Oldval_bankcon4; #endif

The main thing is to perform 3 functions
modifying Bwscon Registers
modifying BANKCON4 Registers
Modify MAC Information

I used to see someone transplant uboot to MINI2440,FCLK,HCLK,PCLK. 1:4:8

The HCLK on MINI2440 is 100MHz, 1 clock 10ns, just twice times larger than the analysis above,

So we can count the clocks/2.
TACS = 1 Clock = 01
TCOs = 2 Clock = 10
TACC = 3 Clock = 010
Tcoh = 2 Clock = 10
Tcah = 1 Clock = 01
TACP = 3 Clock = 01
PMC = Normal (1data) = 00

which is 0x3294.
The note here is to use the wait signal when the TACC is greater than or equal to 4 clock
So will
* ((volatile unsigned int *) s3c2410_bwscon) =
(Oldval_bwscon & ~ (3<<16)) | S3c2410_bwscon_dw4_16 | S3c2410_bwscon_ws4 | S3c2410_bwscon_st4;
* ((volatile unsigned int *) s3c2410_bankcon4) = 0x1f7c;

To
* ((volatile unsigned int *) s3c2410_bwscon) =
(Oldval_bwscon & ~ (3<<16 | S3c2410_bwscon_ws4 | S3C2410_BWSCON_ST4)) | S3c2410_bwscon_dw4_16;
* ((volatile unsigned int *) s3c2410_bankcon4) = 0x3294;

People like it, you can put
#if defined (config_arch_s3c2410)
PRINTK ("Now use the default MAC address:08:90:90:90:90:90/n");
To
#if defined (config_arch_no2410)
PRINTK ("Now use the default MAC address:08:90:90:90:90:90/n");

This will be read DM9000 to get the MAC address, I passed the test, the MAC address is FF:FF:FF:FF:FF:FF
I don't know what will affect the TCP/IP protocol stack.

This is the use of
* ((volatile unsigned int *) s3c2410_bwscon) =
(Oldval_bwscon & ~ (3<<16)) | S3c2410_bwscon_dw4_16 | S3c2410_bwscon_ws4 | S3c2410_bwscon_st4;
* ((volatile unsigned int *) s3c2410_bankcon4) = 0x1f7c;
Time of the delay

Response time is around 0.747

This is the use of
* ((volatile unsigned int *) s3c2410_bwscon) =
(Oldval_bwscon & ~ (3<<16 | S3c2410_bwscon_ws4 | S3C2410_BWSCON_ST4)) | S3c2410_bwscon_dw4_16;
* ((volatile unsigned int *) s3c2410_bankcon4) = 0x3294;
Time of the delay

Visible response time has improved ~ but I do not have a wave meter, so I do not know if this setting will have adverse effects on the DM9000 ~

Turn from: http://blog.chinaunix.net/u1/57901/showart_2023852.html