DMA principle and Experiment

Recently, I was busy with the driver, so I sorted out the basic programming of DMA for S3C2410 and the related register operations for DMA.
I. Principle of DMA access
1. Overview of DMA (driect Memory Access) Access
When the system memory needs to quickly transfer big data between high-speed peripherals or different areas of the memory, the query and interruption methods cannot meet the requirements: DMA is proposed to solve such problems.
(Compared with the query method, the interrupt mode can improve CPU utilization and ensure real-time response to peripherals. However, for high-speed peripherals, the interrupt mode cannot meet the data transmission speed requirements. In the interrupt mode, the breakpoint and the field must be saved for each interruption. When the interruption is returned, the breakpoint and the field must be restored. At the same time, the CPU instruction queue is cleared when the request enters the interrupt and returns from the interrupt. These causes make it difficult for the interrupt mode to meet the transmission speed requirements of high-speed peripherals .)
The DMA method is used to replace the CPU with the DMA controller for a period of time to obtain the control of the bus, so as to realize the fast transmission of a large amount of data between the memory and peripherals or different areas of the memory.

2. DMA Operation Process
1. When the peripherals are ready for DMA transmission, the DMA request signal (dreq) is sent to the DMA controller (DMAc ). After receiving this signal, DMAc sends a bus request signal (hold) to the CPU ).
2. after the CPU completes the current bus operation, it immediately responds to the DMA request signal: First, it gives up control of the bus (including control bus, data bus, and address bus ), then, add the valid hlda signal to DMAc. At this point, the CPU gives up control of the bus, and DMAc gets control of the bus.
3. after obtaining control of the bus, DMAc sends an address signal to the address bus, indicating the memory address used during the transmission process (DMAc has an "Address Register" internally, during the DMA Operation, DMAc automatically modifies the value of the address register to point to the next memory address ). At the same time, a DMA response signal (Dack) is sent to the peripheral to Implement DMA transmission between the peripheral and the memory.
4. During DMA transmission, DMAc sends read/write signals to memory and peripherals.
5. To determine the number of bytes transmitted by data blocks, a "Byte counter" must be provided in DMAc ". At the beginning, the software sets the length of the data block. During the DMA transmission process, when each transmitted byte, the byte counter is reduced by 1, and the value is reduced to 0, the DMA transmission ends.
6. When the DMA process ends, DMAc sends an end signal to the CPU (revoking the hold request) and returns the control of the bus to the CPU.

Ii. DMA Transmission Mode
There are three DMA transmission methods: I/O interface to memory, memory to I/O interface, and memory to memory
1. I/O interface to storage mode
When you want to transfer data from the I/O interface to the memory, the data from the I/O interface uses DMAc to send control signals to the Data Bus D0-D7, at the same time, DMAc sends out the memory unit address and control signal, and writes the data stored on the D0-D7 into the storage unit. This completes the transfer of one byte from the I/O interface to the memory. At the same time, DMAc modifies the content of "Address Register" and "Byte counter.
2. Storage-to-I/O interface method
Similar to the above, during transmission, DMAc sends out the memory address and control signal, read the content of the selected memory unit into the D0-D7 of the data bus, then, DMAc sends out the control signal, write the data to the specified port, and then DMAc modifies the content of "Address Register" and "Byte counter.
3. Storage-to-storage mode
In this mode, the DMA data is transmitted in the "data block" mode (for transmission of multiple bytes in a row, only when the "Byte counter" is reduced to 0 Can the DMA transfer be completed ). First, send the address and control signal of the Memory Source, save the data of the selected memory unit for temporary storage, and then modify the values of "Address Register" and "Byte counter". Then, sends out the address and control signal of the storage target, writes the temporary data to the target area of the storage through the data bus, and finally modifies the content of "Address Register" and "Byte counter, when the value of the byte counter is reduced to zero, a DMA can be ended.

 

Iii. DMA access related operations of S3C2410
1. (This article uses the S3C2410 Development Board) S3C2410 supports 4-channel DMA controller between the system bus and the peripheral bus. Each channel can achieve fast data transmission. Each channel can handle the following four situations:
1. Both the source and target devices are on the system bus AHB.
2. The source device is on the system bus AHB, and the target device is on the peripheral bus APB.
3. The source device is on the peripheral bus APB, and the target device is on the system bus AHB.
4. Both the source and target devices are on the peripheral bus APB.
DMA operations can be initiated through software or hardware. If the dcon register adopts the hardware (H/W) DMA request mode, the DMA controller can select one from the DMA request source of the corresponding channel. If the dcon register selects a software (S/W) DMA request, these DMA request sources will have no significance. The following table lists the DMA request sources.

Nxdreq0 and nxdreq1 represent two external sources. i2ssdo and i2ssdi represent transmission and transmission of IIS respectively.

2. DMA Working Mode
There are two working modes of DMA: single service mode and overall service mode.
In a single service mode, a DMA request completes an atomic operation (operations are uninterrupted ).
In the overall service mode, a DMA request completes a batch of atomic operations until the value of curr_tc is 0, indicating that the overall service is completed.

3. DMA state machine description
DMA can be operated by three FSM (finite state machine, finite state machine) types.
Status 1: initial status. The DMA waits for a DMA request. If the request arrives, it enters status 2. In this phase, the DMA ack and INT req values are 0.
Status 2: In this status, the DMA ack changes to 1, and the counter curr_tc value is loaded from dconn. The DMA ack remains 1 until it is cleared.
State 3: in this state, sub-FSM (sub-state machine) that performs atomic operations on DMA is initialized. Sub-FSM reads data from the source address and writes the data to the target address. For this operation method, the data size and transmission size should be considered. In the overall service mode, this operation is repeated until the counter curr_tc changes to 0, but only once in a single mode. When the sub-FSM completes each atomic operation, the master FSM is counted as curr_tc. In addition, when curr_tc is 0 and dconn [29] is set to 1, the primary FSM sends an int req (interrupt request signal). If any of the following conditions occurs, the DMA ack should be cleared.
(1) in single mode, the three statuses of the master FSM stop after execution and wait for the next DMA request. For each atomic operation, the DMA Ack is set to 1 first, and then cleared to 0.
(2) In the overall service mode, the primary FSM remains in the status of 3 waiting until the curr_tc changes to 0. Therefore, when the DMA Ack is set to 1 during the entire transfer process and the curr_tc is changed to 0, the DMA Ack is cleared to 0.

4. Basic DMA timing
The DMA service means to execute a read/write cycle in the DMA Operation to form a DMA Operation. It is the basic sequence of DMA operations of S3c2410.
After the nxdreq request takes effect and the 2clk periodic synchronization, the nxdack response takes effect, but at least the 3clk periodic delay is required for the DMA controller to gain control of the bus and start data transmission. After the DMA Operation is completed, the xnxdack is set to invalid.

5. There are two types of requests and agreed protocols: Demand and handshake. (Difference: at the end of a transmission, DMA detects the status of the xnxdreq synchronized twice)
Request mode: If xnxdreq is valid, the next transmission starts immediately. Otherwise, it will wait until xnxdreq is valid.
Handshaking mode: If xnxdreq is invalid, the DMA will invalidate the xnxdack during the two synchronization cycles; otherwise, it will wait until xnxdreq is invalid.

6. Transfer size
In an atomic operation of DMA, the Unit mode (transmitting a data size) and brust mode (transmitting four data sizes) can be used ). Set in dcon [28.

7. Data size: the data Bit Width of an atomic operation, which can be 8, 16, or 32. Set in dcon.

 

Iv. DMA Controller
Each DMA channel of S3C2410 has nine control registers and four channels, with 36 registers in total. Each DMA channel has six for controlling DMA transmission and three for monitoring the status of the DMA controller. To perform DMA operations, you must first correctly configure these registers. The following describes related registers. (Because there are too many figures, we haven't posted them here. You can find the corresponding table in Samsung's s3c2401 data sheet)
1. DMA initialization data source (disrc) register group: it corresponds to four registers, which are mainly used to initialize the base address of the transmitted data source.
2. DMA initialization Data Source Control (disrcc) Register: it is mainly used to select the data source location (on APB or on AHB) and determine whether the address is incremented or fixed.
3. DMA initialization target (didst) Register: used to initialize the start address of the transmission target.
4. DMA initialization target control (didstc) Register: it is mainly used to select the target location (on APB or on AHB) and determine whether the address increments are fixed.
5. DMA control (dcon) registers: select request mode or handshake mode, select dreq/Dack synchronization, enable/disable curr_tc interrupt settings, select data size, select single service or overall service mode, select DMA request source and initialize the transmission counters.
6. DMA status (dstat) Register: it is mainly used to read the status of the DMA controller and the current value of the transfer counter.
7. DMA Current Source (dcsrc) Register: it is mainly used to read the value of the current source address of the DMA controller.
8. DMA current target (dcdst) Register: used to read the value of the current target address of the DMA controller.
9. dmasktrig register: used to block interrupt requests from PCI devices.

Iv. DMA Controller
Each DMA channel of S3C2410 has nine control registers and four channels, with 36 registers in total. Each DMA channel has six for controlling DMA transmission and three for monitoring the status of the DMA controller. To perform DMA operations, you must first correctly configure these registers. The following describes related registers. (Because there are too many figures, we haven't posted them here. You can find the corresponding table in Samsung's s3c2401 data sheet)
1. DMA initialization data source (disrc) register group: it corresponds to four registers, which are mainly used to initialize the base address of the transmitted data source.
2. DMA initialization Data Source Control (disrcc) Register: it is mainly used to select the data source location (on APB or on AHB) and determine whether the address is incremented or fixed.
3. DMA initialization target (didst) Register: used to initialize the start address of the transmission target.
4. DMA initialization target control (didstc) Register: it is mainly used to select the target location (on APB or on AHB) and determine whether the address increments are fixed.
5. DMA control (dcon) registers: select request mode or handshake mode, select dreq/Dack synchronization, enable/disable curr_tc interrupt settings, select data size, select single service or overall service mode, select DMA request source and initialize the transmission counters.
6. DMA status (dstat) Register: it is mainly used to read the status of the DMA controller and the current value of the transfer counter.
7. DMA Current Source (dcsrc) Register: it is mainly used to read the value of the current source address of the DMA controller.
8. DMA current target (dcdst) Register: used to read the value of the current target address of the DMA controller.
9. dmasktrig register: used to block interrupt requests from PCI devices.

========================================================== ========================================================== = Detailed Design
The configuration of DMA registers can be found in the S3C2410 Data Manual. For the purpose of the experiment, to achieve DMA transmission between memory, follow these steps:
1. First of all, select the DMA channel;
2. Set the address of the DMA data source (for disrc operations );
3. Set the address control register of the DMA data source (for disrcc operations );
4. Set the DMA target address (for didst operations );
5. Set the address control register of the DMA data source (for didstc operations );
6. initialize the DMA control register (for dcon operations );
7. Open the DMA channel (dmasktrig operation ).
The specific register settings are as follows (assuming dma0 channel is selected ):
Rdisrc0 = srcaddr; // set the address of the DMA data source.
Rdisrcc0 = (0 <1) | (0 <0); // The address increases progressively. The data source address is on AHB.
Rdidst0 = dstadr;
Rdidstc0 = (0 <1) | (0 <0 );
Rdcon0 = tc | (1ul <31) | (1 <30) | (1 <29) | (burst <28) | (1 <27) | (0 <23) | (1 <22) | (DSZ <20) | (TC );
// Define dcon registers HS, AHB, TC interrupt, whole, SW request mode, relaod off
Rdmasktrig0 = (1 <1) | 1; // DMA on (open the DMA channel), sw_trig

Coding design:
1. DMA transfer function void dma_m2m (int ch, int srcaddr, int dstaddr, int TC, int DSZ, int burst)
2. DMA test function void test_dma (void)
3. Test the main function void main (void)
Void dma_m2m (int ch, int srcaddr, int dstaddr, int TC, int DSZ, int burst)
{
Int I, time;
Volatile u32 memsum0 = 0, memsum1 = 0;
DMA * pdma;
Int length = tc * (burst? ) * (DSZ = 0) + (DSZ = 1) * 2 + (DSZ = 2) * 4 );

Uart_printf ("[DMA % d mem2mem test]/n", CH );
Switch (CH)
{
Case 0:
Pisr_dma0 = (INT) dma0done; // interrupt service program of dma0
Rintmsk & = ~ (Bit_dma0); // allows dma0 interruption
Pdma = (void *) 0x4b000000;
Break;
Case 1:
Pisr_dma1 = (INT) dma1done;
Rintmsk & = ~ (Bit_dma1 );
Pdma = (void *) 0x4b000040; break;
Case 2:
Pisr_dma2 = (INT) dma2done;
Rintmsk & = ~ (Bit_dma2 );
Pdma = (void *) 0x4b000080; break;
Case 3:
Pisr_dma3 = (INT) dma3done;
Rintmsk & = ~ (Bit_dma3 );
Pdma = (void *) 0x4b1_c0; break;
}


Uart_printf ("DMA % d % 8xh-> % 8xh, size = % XH (TC = % XH), DSZ = % d, burst = % d/N", CH, srcaddr, dstaddr, length, TC, DSZ, burst );
Uart_printf ("initialize the SRC./N ");

For (I = srcaddr; I <(srcaddr + length); I + = 4)
{
* (U32 *) I) = I ^ 0x55aa5aa5;
Memsum0 + = I ^ 0x55aa5aa5;
}

Uart_printf ("DMA % d start/N", CH );

Dmadone = 0;

Rdisrc0 = srcaddr;
Rdisrcc0 = (0 <1) | (0 <0); // Inc, AHB source from AHB
Rdidst0 = dstaddr;
Rdidstc0 = (0 <1) | (0 <0); // Inc, AHB for AHB
Rdcon0 = tc | (1ul <31) | (1 <30) | (1 <29) | (burst <28) | (1 <27) |/
(0 <23) | (1 <22) | (DSZ <20) | (TC );
// HS, AHB, TC interrupt, whole, SW request mode, relaod off
// Rintmsk = ~ (Bit_dma0 );
Rdmasktrig0 = (1 <1) | 1; // DMA on, sw_trig

// Timer_start (3); // 128us resolution
While (dmadone = 0 );
// Time = timer_stop ();

Printf ("DMA % d end/N", CH );

// Uart_printf ("DMA transfer done. Time = % F, % FMB/S/N", (float) Time/onesec3,
// Length/(float) Time/onesec3)/1000000 .);
Rintmsk | = (bit_dma0 | bit_dma1 | bit_dma2 | bit_dma3 );

For (I = dstaddr; I <dstaddr + length; I + = 4)
{
Memsum1 + = * (u32 *) I) = I ^ 0x55aa5aa5;
}

Uart_printf ("memsum0 = % x, memsum1 = % x/N", memsum0, memsum1 );
If (memsum0 = memsum1)
Uart_printf ("DMA test result -------- o. k./N ");
Else
Uart_printf ("DMA test result -------- Error !!! /N ");
}

Void test_dma (void)
{
// DMA ch 0
Dma_m2m (0, 0x31020000,0x31020000 + 0x80000,0x80000,0, 0); // byte, single
}

Void main (void)
{
Int I;
U8 key;
U32 mpll_val = 0;

Port_init (); // port Initialization
Isr_init (); // interrupt Initialization
Uart_init (115200); // The initial baud rate of the serial port is.
Uart_select (0); // selected serial port 0
Changeclockdivider (); //
Changempllvalue (0xa1, 0x3, 0x1); // fclk = 202.8 MHz

I = 0;
Uart_printf ("/nbegin to start UART test, OK? (Y/N)/n ");
Key = uart_getch ();

If (Key = 'y' | key = 'y ')
Test_dma ();
Else
Uart_printf ("/Noh! You quit the test! /N ");
Uart_printf ("/n ======= UART test end =======/N ");
}