[Documentation]. Amy electronics-logical gate circuit

ArticleDirectory

• Reader's assumptions
• Content
• Summary
• Secondary reading
• Reference

Reader's assumptions

Mastered:

• Programmable Logic Basics
• Base on OpenGL
• Verilog us II Getting Started Guide designed with OpenGL
• ModelSim Getting Started Guide designed with OpenGL

 

Content 1 Basic door circuit 1.1 Structured description

1. Use Quartus II to create a project logic_gates. The top-level module is named logic_gates, as shown in Figure 1.1.

Figure 1.1 create a project logic_gates

 

2. Enter the followingCode.

 
'Timescale 1ns/1 nsmodule logic_gates (input IA, input IB, output Oand, output oor, output onot); and and_inst (Oand, IA, IB); or or_inst (oor, IA, IB); not not_inst (onot, Ia); endmodule
 

10th ~ The 12 rows use the gate-level primitive, respectively, and the door, or the door and the non-door.

And and_inst (Oand, IA, IB); or or_inst (oor, IA, IB); not not_inst (onot, Ia );
 

 

3. Because it is a basic door circuit, we compile it directly. After the compilation is successful, selectTools> netlist viewers> RTL ViewerView the RTL view after the project is integrated, as shown in Figure 1.2.

Figure 1.2 RTL View

 

4. Compile testbench. Configure testbench, 1.3, in Quartus II, as described in the Verilog us II Getting Started Guide with the design of the language.

 
'Timescale 1ns/1 nsmodule logic_gates_tb; Reg I _a; Reg I _ B; wire o_and; wire o_or; wire o_not; initialbegin I _a = 0; #40 I _a = 1; #40 I _a = 0; #40 I _a = 1; #40 I _a = 0; endinitialbegin I _ B = 0; #40 I _ B = 0; #40 I _ B = 1; #40 I _ B = 1; #40 I _ B = 0; endlogic_gates logic_gates_inst (. ia (I _a ),. IB (I _ B ),. oand (o_and ),. OOR (o_or ),. onot (o_not); endmodule
 

11th ~ 18 lines and 20th ~ The initial blocks of the 17 rows are used to motivate I _a and I _ B respectively.Note that the left-hand side signals in the initial block must be declared as Reg type.In addition, the statements in the initial block are executed sequentially. #40 indicates that the signal changes at 40 units of time. The first sentence after begin indicates the initial value when the time unit is 0.Note that the initial block is not suitable for use in comprehensive HDL code and is only suitable for simulation.

 
Initialbegin I _a = 0; #40 I _a = 1; #40 I _a = 0; #40 I _a = 1; #40 I _a = 0; endinitialbegin I _ B = 0; #40 I _ B = 0; #40 I _ B = 1; #40 I _ B = 1; #40 I _ B = 0; End
 

Last 29th ~ 35 lines, sample the logic_gates module.

 
Logic_gates logic_gates_inst (. Ia (I _a),. IB (I _ B),. Oand (o_and),. oor (o_or),. onot (o_not ));
 

 

Figure 1.3 configure testbench

 

5. In Quartus II, selectTools> run rda simulation tools> eda rtl simulationTo perform RTL simulation. In the displayed modelsim_altera window, zoom in and zoom out the waveform to check whether the result is consistent, as shown in waveform 1.4.

Figure 1.4 function simulation waveform

 

6. In Quartus II, selectTools> run rda simulation tools> gate level simulationFor door-level simulation, 1.5.

Figure 1.5 door-level simulation waveform

 

After careful observation, we will find that the initial values of o_and, o_or, and o_not are not fixed X, and the expected values will be delayed for a period of time. The specific door-level latency varies depending on the hardware. However, RTL simulation does not have this latency. Therefore, the RTL simulation is correct, which does not mean that the actual effect is correct. the correctness of the gate simulation is also an important factor to evaluate.

 

1.2 stream description

1. Replace the previous logic_gates.v:

 
'Timescale 1ns/1 nsmodule logic_gates (input IA, input IB, output Oand, output oor, output onot); assign Oand = IA & Ib; assign oor = Ia | Ib; assign onot = ~ IA; endmodule
 

10th ~ Line 12 uses bitwise operators to process and or not. This is a common method to describe a combination of logical circuits.

 
Assign Oand = IA & Ib; assign oor = Ia | Ib; assign onot = ~ IA;
 

 

2. Repeat Step 1.1 to view the integrated RTL view of the project, as shown in step 3rd.

Figure 1.6 RTL View

 

3. Repeat Step 1.1 of Step 1.1 to view the simulation waveform, as shown in step 5th.

Figure 1.7 function simulation waveform

 

1.3 behavior description

1. Replace the previous logic_gates.v:

 
'Timescale 1ns/1 nsmodule logic_gates (input IA, input IB, output Reg Oand, output Reg oor, output Reg onot); always @ (*) Begin Oand = IA & Ib; oor = Ia | Ib; onot = ~ IA; endendmodule
 

10th ~ 15 rows. In the always block, use the behavior description method to implement or non-gate.Note: any signal that appears in the always block and on the left side must be declared as Reg type, whether it is mapped to a register or a node or not.This is another way to describe a combined logical circuit.Note: When describing a logical combination circuit, use the blocking assignment method (=) in the always block ).

 
Always @ (*) Begin Oand = IA & Ib; oor = Ia | Ib; onot = ~ IA; End
 

 

Always @ (sensitive signal), and Tilde 2001 provides a simpler method: Always @ (*). The synthesizer automatically adds sensitive signals. This is the case with rows 10th.

Always @(*)
 

 

2. Repeat Step 1.1 to view the integrated RTL view of the project, as shown in step 3rd.

Figure 1.8 RTL View

 

3. Repeat Step 1.1 of Step 1.1 to view the simulation waveform, as shown in step 5th.

Figure 1.9 function simulation waveform

 

Conclusion 1.4

Through 1.1 ~ In practice 1.3, we found that the effect of the door circuits corresponding to the three descriptions is consistent.

 

2 three-state gate circuit

A three-state gate, that is, its output is not only related to the input, but also controlled by the enabling signal. After enabling, the output is equal to the input. If not enabled, the output is a high-impedance state.

1. Replace logic_gates.v:

 
'Timescale 1ns/1 nsmodule logic_gates (input IA, input ienable_n, output otristate); assign otristate = (~ Ienable_n )? IA: 1 'bz; endmodule
 

Line 3, ienable_n indicates the enable signal, which is effective at a low level. It is often indicated by the suffix _ n.

 
Input ienable_n,
 

 

8th rows, (condition )? (When the condition is true): (if the condition is false, the value is used here to describe the three-state gate. If the enable signal is low, the output equals to the input. If the enable signal is high, the output is of high resistance.

 
Assign otristate = (~ Ienable_n )? IA: 1 'bz;
 

 

2. recompile the project and view the integrated RTL view, as shown in figure 2.1.

Figure 2.1 three-state gate RTL View

 

3. Replace logic_gates_tb.v:

 
'Timescale 1ns/1 nsmodule require; Reg I _a; Reg I _enable_n; wire o_tri_state; initialbegin I _a = 0; #40 I _a = 1; #40 I _a = 0; #40 I _a = 1; endinitialbegin I _enable_n = 1; #20 I _enable_n = 0; #40 I _enable_n = 1; #20 I _enable_n = 0; endlogic_gates logic_gates_inst (. ia (I _a ),. ienable_n (I _enable_n ),. otristate (o_tri_state); endmodule
 

 

4. Check whether the functional simulation and door-level simulation are correct, as shown in figure 2.2 and Figure 2.3.

Figure 2.2 function simulation waveform

 

Figure 2.3 Door-level simulation waveform

 

3 bidirectional door circuit

Bidirectional door circuit, which can be input and output, is commonly used in bidirectional ports. In fact, this two-way method is time-division multiplexing and cannot be used for input and output at the same time. Therefore, it works as a ticket: when the input is used, the output must be disabled; when the output is used, you must enable the output function.Note: In general, in the sub-module, split the two-way port into two signals: Input and Output. In the end, the two-way port is added only to the top-layer module.

1. Replace logic_gates.v:

 
'Timescale 1ns/1 nsmodule logic_gates (input IA, input iw_r, output OB, inout IOC); assign IOC = iw_r? IA: 1 'bz; assign Ob = (~ Iw_r )? IOC: 1 'bz; endmodule
 

9th ~ Line 10 uses two three-state gates to implement two-way door circuit.

 
Assign IOC = iw_r? IA: 1 'bz; assign Ob = (~ Iw_r )? IOC: 1 'bz;
 

The following description is also common in the description of bidirectional data bus in various memory circuits.

 
Assign IOC = iw_r? IA: 1 'bz; assign Ob = IOC;
 

 

2. recompile the project and view the integrated RTL view, as shown in Figure 3.1.

Figure 3.1 RTL View

 

3. This testbench is a little troublesome. Here we use two testbench to test the Read and Write simulation of two-way ports successively. Perform output testing first. Replace logic_gates_tb.v:

 
'Timescale 1ns/1 nsmodule logic_gates_tb; Reg I _a; Reg I _w_r; wire io_c; initialbegin I _a = 0; #40 I _a = 1; #40 I _a = 0; #40 I _a = 1; endinitialbegin I _w_r = 1; #20 I _w_r = 0; #40 I _w_r = 1; #20 I _w_r = 0; endlogic_gates logic_gates_inst (. ia (I _a ),. iw_r (I _w_r ),. ob (),. IOC (io_c); endmodule
 

 

4. Check whether the simulation of the output test function and the door-level simulation are correct, as shown in figure 2.2 and Figure 2.3.

Figure 2.2 output test function simulation waveform

 

Figure 2.3 output gate-level simulation waveform

 

5. Perform the input test again. Replace logic_gates_tb.v with the following:

'Timescale 1ns/1 nsmodule; Reg I _w_r; wire o_ B; wire io_c; Reg io_c_reg; initialbegin I _w_r = 1; #20 I _w_r = 0; #40 I _w_r = 1; #20 I _w_r = 0; endinitialbegin io_c_reg = 0; #40 io_c_reg = 1; #40 io_c_reg = 0; #40 io_c_reg = 1; endassign io_c = io_c_reg; logic_gates limit (. ia (),. iw_r (I _w_r ),. ob (o_ B ),. IOC (io_c); endmodule
 

 

6. Increase or decrease the signal appropriately and check whether the output test function simulation and door-level simulation are correct, as shown in Figure 2.4 and Figure 2.5.

Figure 2.4 input test function simulation waveform

 

Figure 2.5 door-level simulation waveform of input test

 

Summary

This is a simple article that describes three common door circuits. It is hoped that beginners can learn and master the circuit by describing the circuit using HDL, and then observe its comprehensive RTL view to check whether it is consistent with the required circuit, and test its Input Waveform through simulation. It is true that learning FPGA is not a simple task. In addition to a solid learning attitude, we also need to learn more and learn more. Don't worry, take it easy. Maybe one day, you will find that the original circuit is in our hearts.

 

Secondary reading

1. Wikipedia. Logic Gate

2. actel. actel HDL coding style guide-actel HDL Coding

 

Reference

1. Liu fuqi, Liu Bo. detailed introduction to the example of designing the applications of the OpenGL. E-Industry Press

 

See also

[Study FPGA/FPGA with Amy]. [logical experiment document serialization plan]