[Documentation]. Amy electronics-parameters and constants

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• 1 constant
• 2 parameters
• 3 using parameters in Verilog-1995

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Mastered:

• Programmable Logic Basics
• Base on OpenGL
• Verilog us II Getting Started Guide designed with OpenGL
• ModelSim Getting Started Guide designed with OpenGL

Content 1 constant

HDLCodeConstants are often used at the boundary of expressions and arrays. These values are fixed within the module and cannot be modified. A good design practice is to replace these hard literal with symbolic constants, so that the code is clear and easy to maintain and modify later. In OpenGL, you can use localparam (local parameter) to declare constants. For example, we can declare the Bit Width and data range of a data bus as follows:

 
Localparam data_widyh = 8, data_range = 2 ** data_widyh-1;
 

Or define a symbolic port name:

 
Localparam uart_port = 4 'b0001, LCD _port = 4 'b0010, mouse_port = 4' b0100;
 

The expressions in the Declaration, such as the 2 ** DATA_WIDTH-1, are calculated during pre-compilation, so it does not reference any physical circuit. Generally, we use uppercase letters to represent constants.

Can be used to describe constants. Consider the code of a sub-device that brings in bits. To correctly execute the addition operation, you can manually extend the input value to one bit and take the highest bits of the sum as the carry. The Code is as follows:

Code 1 use the hard literal Calculator

 
Module adder_carry_hard_lit (input [3: 0] A, input [3: 0] B, output [3: 0] sum, output cout // carry output); // signal declarationwire [4: 0] sum_ext; // bodyassign sum_ext = {1 'b0, a} + {1 'b0, B}; assign sum = sum_ext [3:0]; assign cout = sum_ext [4]; endmodule
 

The code shows a 4-bit multiplier. Hard literal, that is, hard text, such as 3 and 4 used to represent the data range, wire [4:] And sum_ext [], and the highest position sum_ext [4]. If we need to change it to an 8-bit calculator, We need to manually modify these hard literal for a long time. If the code is complex and references these hard literal in multiple places, modifying it will be a painful task and may cause unnecessary errors.

To improve code readability, we can use a symbolic constant, for example, using N to represent the number of bits of the calculator. The modified code is as follows:

Code 2 use a constant Calculator

Module adder_carry_local_par (input [3: 0] A, input [3: 0] B, output [3: 0] sum, output cout // carry output); // constant declarationlocalparam n = 4, n1 = n-1; // signal declarationwire [4:0] sum_ext; // bodyassign sum_ext = {1 'b0, a} + {1 'b0, B }; assign sum = sum_ext [N1: 0]; assign cout = sum_ext [N]; endmodule
 

Constants make the code easier to understand and maintain.

2 parameters

The module of the Tilde can be instantiated as part of a larger module. Parameters are provided for the module to transmit information. This mechanism makes the module more common and reusable, so its function is similar to a constant.

In the Verilog-2001, the parameter definition area can be added to the module's header, that is, before the port declaration. The simple syntax is as follows:

 
Module [module_name] # (parameter [parameter_name] = [default_value],..., [parameter_name] = [default_value]) (... // I/O port Declaration );
 

For example, you can modify the width of the previously added sub-device to the format specified by parameters.

Code 3 use the parameter Calculator

Module adder_carry_para # (parameter n = 4) (input [N-1: 0] A, input [N-1: 0] B, output [N-1: 0] sum, output cout // carry output); // constant declarationlocalparam n1 = n-1; // signal declarationwire [N: 0] sum_ext; // bodyassign sum_ext = {1 'b0, a} + {1 'b0, B}; assign sum = sum_ext [N1: 0]; assign cout = sum_ext [N]; endmodule
 

The default value of N parameter is 4. After N is declared, it can be used in the port declaration and module body like a constant.

If later, this calculator is used as a component of other code, we can specify the desired value to the parameter during component Instantiation to abolish the default value. Parameters can be specified by name or sequence list. In general, I specify parameters by name. See the Code:

Code 4 Examples of adding sub-Devices

 
Module adder_inst (input [3: 0] A4, B4, output [3: 0] sum4, output C4, input [7: 0] A8, B8, output [7: 0] sum8, output C8 ); // instantiate 8-bit adderadder_carry_para #(. N (8) a_inst1 (. A (A8 ),. B (B8 ),. sum (sum8 ),. cout (C8); // instantiate 4-bit adderadder_carry_para a_inst2 (. A (A4 ),. B (B4 ),. sum (sum4 ),. cout (C4); endmodule
 

Parameters provide a mechanism for creating code that can be stretched, so that the "width" of the circuit can be adjusted as required. Writing code in this way can make the design more reusable.

3 using parameters in Verilog-1995

Localparam keywords, header declarations, passing information to the module by specifying parameters by name are new features of the Verilog-2001. In the Verilog-1995, the parameter is declared after the actual header, and can only be redefined through a sequential list scheme or a defparam statement. Furthermore, a constant must be declared as a parameter, although it should not be redefined. The code described above using the Verilog-1995 syntax is as follows:

Code 5 using the Verilog-1995 Parameters

 
Module adder_carry_95 (a, B, sum, cout); parameter n = 4; // parameter declared before the portparameter n1 = n-1; // No localparam in Verilog-1995input [N1: 0] A, B; Output [N1: 0] sum; Output cout; // signal declarationwire [N: 0] sum_ext; // bodyassign sum_ext = {1 'b0, a} + {1 'b0, B}; assign sum = sum_ext [N1: 0]; assign cout = sum_ext [N]; endmodule
 

When a component is instantiated, parameters can only be redefined using the sequence list scheme, for example:

 
Adder_carry_95 # (8, 7) a_inst1 (. A (A8),. B (B8),. sum (sum8),. cout (C8 ));
 

Or use the defparam statement, for example:

Defparam a_inst2.n = 8; defparam a_inst2.n1 = 7; adder_carry_95 a_inst2 (. A (A8),. B (B8),. sum (sum8),. cout (C8 ));
 

The Verilog-1995 solution is lengthy and cumbersome and may produce some subtle errors, so it is not recommended.

Reference

1 Pong P. Chu. FPGA prototyping by Xilinx examples: Xilinx Spartan-3 version. Wiley

See also

[Study FPGA/FPGA with Amy]. [logical experiment document serialization plan]