[Documentation]. Amy electronics-register

ArticleDirectory

• 1 register
• 2 register files
• 3. FPGA chip storage module

Reader's assumptions

Mastered:

• Programmable Logic Basics
• Base on OpenGL
• Verilog us II Getting Started Guide designed with OpenGL
• ModelSim Getting Started Guide designed with OpenGL

Content 1 register

Registers are a set of D triggers controlled by the same clock and reset signal. Like the D-FF, registers have selectable Asynchronous Reset signals and synchronous enable signals.CodeThe same as the D-FF, but the input and output signals of the array data type need to be affirmed.

Code 1 8-bit register with Asynchronous Reset

 
Module reg_asyn_rst (// global clock and Asyn reset input CLK, input rst_n, // I/O interface input [7:0] D, output Reg [7:0] Q ); // bodyalways @ (posedge CLK, negedge rst_n) if (! Rst_n) q <= 0; else q <= D; endmodule
 

2 register files

A register file is a set of registers with an input port and one or more output ports. Write address signal, w_addr, specifying where data is stored; read address signal, r_addr, specifying where data is retrieved. Register files are generally used for fast and temporary data storage. Code 2 shows a parameterized register file. The data line width is B and the address line width is W. Two parameters are defined: W specifies the address line width, indicating that there are 2 ^ W characters in this file; B specifies the number of characters in each word.

Code 2 parameterized Register File

 
Module reg_file # (parameter B = 8, // width of the Data Bus parameter W = 2 // width of the address bus) (// global clock input CLK, // register file interface input wr_en, input [W-1: 0] w_addr, input [W-1: 0] r_addr, input [B-1: 0] w_data, output [B-1: 0] r_data); // signal declaration Reg [B-1: 0] array_reg [2 ** W-1: 0]; // body // write operation always @ (posedge CLK) if (wr_en) array_reg [w_addr] <= w_data; // read operationassign r_data = array_reg [r_addr]; endmodule
 

Row 3, we noticed a new data type, two-dimensional array data type. ** In this example, it indicates the Multiplication Side.

 
Reg [B-1: 0] array_reg [2 ** W-1: 0];
 

First, it indicates that the array_reg variable has [2 ** W-1: 0] elements, and the data type for each element is Reg [B-1: 0]. Second, this variable requires an index to access elements in the array, such as reg_array [w_addr].

3. FPGA chip storage module

In the Cyclone ii fpga, each le includes a D-FF With Asynchronous Reset and synchronous enabling, but also carries a 4-input LUT. If you simply use le to do a lot of storage work, it will waste a lot of le. In this case, you can consider using a built-in ram block, such as the m4k in cycloen II or the m9k in a more advanced chip. Relevant issues will be discussed in the future.

Reference

1 Pong P. Chu. FPGA prototyping by Xilinx examples: Xilinx Spartan-3 version. Wiley

See also

[Study FPGA/FPGA with Amy]. [logical experiment document serialization plan]