[Documentation]. Amy electronics-triggers and latches

ArticleDirectory

• 1 D Trigger
•  
• 2 t trigger
• 3-Gate D-latches

Reader's assumptions

Mastered:

• Programmable Logic Basics
• Base on OpenGL
• Verilog us II Getting Started Guide designed with OpenGL
• ModelSim Getting Started Guide designed with OpenGL

Content 1 D Trigger

Here, we start learning the time series logic from the D Trigger. A lot of triggers will be designed in the digital circuit class. Here we only use simple D triggers and T triggers as examples. For more information about the truth table, see the digital circuit reference.

1.1 Synchronous Reset D Trigger

First, you need to understand the difference between Synchronous Reset and Asynchronous Reset. The so-called Synchronous Reset refers to the Synchronous Reset signal, that is, the reset signal is valid only when the required clock edge is reached, and the reset signal is invalid at other times. In general, as long as the reset signal lasts longer than a clock cycle, the correct reset can be ensured.

Figure 1.1.1 Synchronous Reset D Trigger

Code1.1 Synchronous Reset D-FF

 
Module d_ff (input CLK, input rst_n, input D, output Reg Q, output Q_n); always @ (posedge CLK) if (! Rst_n) q <= 1 'b0; else q <= D; assign Q_n = ~ Q; endmodule
 

In Quartus II, choose tools> nestlist viewers to view RTL viewer and technology map viewer (post-mapping ).

Figure 1.1.2 synchronization reset D-ff rtl View

 

Figure 1.1.3 Synchronous Reset of D-FF technology map viewer (post-mapping)

As shown in figure 1.1.3, double-click Q ~ After the value is 0, logic_cell_comb (8888) is mapped to the gate. Looking at figure 1.1.2 and figure 1.2.3, we find that the RTL view cannot accurately reflect the circuit described by the HDL. At this time, we use the technology map viewer (post-mapping) you can more accurately view what underlying circuits are mapped to the HDL. The results shown in this figure are consistent with the expected results.

Code 1.1.2 Synchronous Reset of the D-FF testbench

 
'Timescale 1ns/1 nsmodule d_ff_tb; Reg CLK, rst_n; Reg D; wire Q, Q_n; initial begin CLK = 0; forever #20 CLK = ~ CLK; endinitial begin rst_n = 0; #10 rst_n = 1; #50 rst_n = 0; #60 rst_n = 1; endinitial d = 1; initial #200 $ stop; d_ff d_ff_inst (. CLK (CLK ),. rst_n (rst_n ),. D (D ),. q (Q ),. q_n (Q_n); endmodule
 

Figure 1.1.4 simulation waveform of Synchronous Reset Function

Figure 1.1.4: at t = 70ns, the reset signal is low, but not on the rising edge of the clock. The output Q is not reset. at t = 100ns, the reset signal is low, at this time, the clock is really on the rising edge, so the output Q can be reset. At the same time, it should be noted that after the reset signal is invalid, the Q output can be stopped only after the next rising edge of the clock has arrived. This is the so-called Synchronous Reset D Trigger.

Figure 1.1.5 synchronized reset gate-level simulation waveform

Observe 1.1.5 and we find that, unlike function simulation, the output Q is automatically reset upon power-on. The Reset is stopped only when Q is output when the reset signal of the next clock rising edge is detected as high; the waveforms at other times are consistent with functional simulation.

1.2 Asynchronous Reset D Trigger

Asynchronous Reset: no matter whether the clock edge arrives or not, the reset signal will be reset as long as the reset signal is effective.

Figure 1.2.1 Asynchronous Reset D-FF

Code 1.2.1 Asynchronous Reset D-FF

 
Module d_ff (input CLK, input rst_n, input D, output Reg Q, output Q_n); always @ (posedge CLK, negedge rst_n) if (! Rst_n) q <= 1 'b0; else q <= D; assign Q_n = ~ Q; endmodule
 

Unlike the D-FF code of Synchronous Reset, the reset signal of the descent edge is added to the sensitive signal list.

Figure 1.2.2 RTL view of Asynchronous Reset D-FF

Use testbench of code 1.1.2 to compile and view the simulation waveforms before and after it. After observation, we found that as long as the Asynchronous Reset signal is valid, the output Q is reset immediately.

Figure 1.2.3 simulation waveform of Asynchronous Reset D-FF

2 t trigger

Figure 2.1 T-FF symbols

T triggers can be transformed from D triggers and JK triggers. When the rising edge of the clock is reached, if T = 0, the secondary State is consistent with the current state. If T = 1, the secondary State is the current state.

Code 2.1 T-FF

 
Module t_ff (input CLK, input rst_n, input T, output Reg Q, output Q_n); always @ (posedge CLK, negedge rst_n) if (! Rst_n) q <= 1 'b0; else if (t) q <=! Q; assign Q_n = ~ Q; endmodule
 

Note 9th ~ Else is missing for the process statements in the always block of Line 11.

 
Always @ (posedge CLK, negedge rst_n) if (! Rst_n) q <= 1 'b0; else if (t) q <=! Q;
 

In fact, it is equivalent to the following statement, that is, the statement implied by else to retain the current state can be omitted.

 
Always @ (posedge CLK, negedge rst_n) if (! Rst_n) q <= 1 'b0; else if (t) q <=! Q; else q <= Q;
 

Use tools> netlist viewers> technology map viewer (post-mapping) to view the specific circuit in which the preceding HDL is translated.

Figure 2.2 technology map viewer for T-FF

Code 2.2 T-FF testbench

 
'Timescale 1ns/1 nsmodule t_ff_tb; Reg CLK, rst_n; Reg T; wire Q, Q_n; // ++ // call parameter clk_period = 20 again for clock and reset excitation, reset_time = 10; initial CLK = 0; initial forever # (clk_period/2) CLK = ~ CLK; initial rst_n = 0; initial # reset_time rst_n = 1; // ---------------------------------------- initial T = 0; initial forever #25 t = {$ random} % 2; initial #200 $ stop; t_ff t_ff_inst (. CLK (CLK ),. rst_n (rst_n ),. T (t ),. q (Q ),. q_n (Q_n); endmodule
 

In row 3, $ random is called to generate a random number. $ Random % n randomly generates signed integers between {-n + 1, n + 1}, and {$ random} % n randomly generates positive integers between {0, n-1. 0 ~ will be randomly generated here ~ A positive integer of 1.

 
Initial forever #25 t = {$ random} % 2;
 

Figure 2.3 RTL-level simulation waveform of T-FF

We can see that when the rising edge of the clock is reached, if T = 0, the secondary State is consistent with the current State; if T = 1, the secondary State is the current state. The flip word is toggle, that is, the source of the T-FF name.

3-Gate D-latches

Figure 3.1 d-latch symbols

The output Q changes with the input d only when the CLK is high. When the CLK is low, the status of the lock will be frozen and the output Q will remain unchanged, until the CLK is restored to a high level.

Code 3.1 Gates D-latches

 
Module d_latch (input CLK, input rst_n, input D, output Reg Q); always @ * If (! Rst_n) q <= 1' B0; else if (CLK = 1' B) q <= D; endmodule
 

Figure 3.2 technology mapping viewer of the Gate D lock

Code 3.2: access the testbench of the D-Lock

'Timescale 1ns/1 nsmodule d_latch_tb; Reg CLK, rst_n; Reg D; wire Q; // ++ // call parameter clk_period = 20 again for clock and reset excitation, reset_time = 10; initial CLK = 0; initial forever # (clk_period/2) CLK = ~ CLK; initial rst_n = 0; initial # reset_time rst_n = 1; // ---------------------------------------- initial begin D = 0; repeat (10) #11 d = ~ D; #10 $ stop; endd_latch d_latch_inst (. CLK (CLK),. rst_n (rst_n),. D (D),. Q (q); endmodule
 

Note that in Row 3, repeat (n) indicates that the following (in begin-end) Statement is executed n times consecutively. This is 10 times.

 
Repeat (10) #11 d = ~ D;
 

Figure 3.3 RTL-level simulation waveform of the Gate D-Lock

When the clock is high, Q changes with D, and when the clock is high, the Q value remains unchanged.

Figure 3.4 shows the basic time series parameter model of the Gate D Trigger. Before the arrival of the CLK descent, the shortest time for D to be stable is calledCreation Time of the latch t_suThe shortest time for D to remain stable after the descent edge of CLK is calledSynchronization duration t_h.

Figure 3.4 basic timing parameters of a Gate D Trigger

4 sub-steady state

Figure 4.1 Asynchronous Reset D-FF

Figure 4.2 timing parameters of a trigger

As shown in Figure 4.2, D must maintain a stable shortest time before the rising edge of CLK arrives.Trigger creation time t_suAfter the rising edge of CLK arrives, D must maintain a stable shortest timeTrigger holding time t_h. If t_su or t_h cannot strictly meet the requirements of the circuit, the trigger enters an unstable state, that is, the sub-steady state. From the rising edge of CLK, the time required for Q to change with D isPropagation delay from CLK to Q t_cq.

Conclusion

This article ends now. Some related concepts will be discussed later.

Reference

1. http://www.asic-world.com/examples/verilog/flip_flop.html

2. Stephen Brown, Zvonko vranesic. Fundamentals of digital logic with OpenGL design 2nd edition. Mc Graw Hill

See also

[Study FPGA/FPGA with Amy]. [logical experiment document serialization plan]