Dream back----Universal registers for 32-bit CPUs and 64-bit CPUs

1 32-bit Intel CPU general-purpose registers

32-bit CPUs include 4 data registers (EAX, EBX, ECX, and edx), 2 variable-address and pointer registers (ESI and EDI), 2 pointer registers (ESP and EBP), 6 segment registers (ES, CS, SS, DS, FS, and GS) ; 1 instruction Pointer Register (EIP), 1 flag Register (eflags).

Of these, 4 data registers and 2 address and pointer registers and 2 pointer registers are also common to us.

1.1 Data Registers

Data registers are primarily used to save information such as operands and operation results, thus saving the time required for the read operation to occupy the bus and access memory. The 32-bit CPU has 4 general-purpose registers of 32-bit eax, EBX, ECX, EDX. Access to low 16-bit data does not affect data that is 16 bits high. These low 16-bit registers are named: AX, BX, CX, and DX, which is consistent with the naming of 16-bit CPUs. 4 16-bit registers can be divided into 8 independent 8-bit registers (Ax:ah-al, BX:BH-BL, CX:CH-CL, DX:DH-DL). Each register has its own name and can be accessed independently. Programmers can use this "can-do" feature of data registers to handle word and byte information flexibly.

Register Ax and Al are often called accumulators (accumulator), and operations with accumulators may take less time. Accumulator can be used for multiplication, divide, input, output and other operations, it is used very frequently.

The register BX is called the Base register, which acts as a memory pointer to use.

The register CX is called the Counter Register (Count register), which is used to control the number of loops in the loop and string operations; In a bit operation, when moving multiple bits, CL is used to indicate the number of bits shifted.
The register DX, called the data register, can participate in the operation as the default operand or the port address of the I/O in the multiplication and divide operation.

In a 16-bit CPU, AX, BX, CX, and DX cannot hold the address of a storage unit as a base address and a variable address register, but in a 32-bit CPU, its 32-bit registers eax, EBX, ECX, and edx can not only transmit data, but also hold the result of the arithmetic logical operation of the staging data, as well as pointer registers So these 32-bit registers are more versatile.

1.2 Variable address register

The 32-bit CPU has 2 32-bit general-purpose registers ESI and EDI. Its low 16 bits correspond to the SI and di in the 16-bit CPU, and access to low 16-bit data does not affect the high 16-bit data. Registers esi, EDI, Si, and di are referred to as the variable-address registers (Index register), which are primarily used to hold the offset of the storage unit within the segment. They can be used to address a variety of memory operations, and to provide convenient access and storage units for different types of addresses. The variable address register is an integral 8-bit register. As a general register, the operands and results of arithmetic logic operations can also be stored. They can be used as a general memory pointer. During the execution of the string manipulation instructions, there are specific requirements and special features.

1.3 Pointer Register

The 32-bit CPU has 2 32-bit general-purpose registers EBP and esp. Its low 16-bit corresponding to the 16-bit CPU of the BP and SP, the low 16-bit data access, does not affect the high 16-bit data. Register EBP, ESP, BP, SP, known as the Pointer Register (Pointer register), mainly used to store the offset of the stack memory units, which can be used to achieve the address of a variety of memory operations, in order to access the storage unit in a different format to facilitate. The pointer register is an integral 8-bit register. As a general register, the operands and results of arithmetic logic operations can also be stored. They are primarily used to access storage units within the stack and provide for:

BP is the base pointer (base Pointer) register, which can directly access the data in the stack;

The SP is a stack-Pointer register that can only access the top of the stack.

1.4 Segment Registers

Segment registers are set according to the management mode of memory fragmentation. The physical address of a memory unit is a combination of the value of the segment register and an offset, which can be combined into a memory address of a larger physical space that can be accessed with a value of two less digits.

The segment registers inside the CPU are as follows:

cs--Code Segment Register, whose value is the segment value of the code snippet;
ds--Data Segment Register, whose value is the segment value of the data segment;
es--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The ss--stack segment register (stack Segment register), whose value is the segment value of the stack segment;
fs--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The gs--additional segment register (Extra Segment register), whose value is the segment value of the additional data segment.

In a 16-bit CPU system, it has only 4 segment registers, so the program can be accessed directly at most 4 segments in use at any time, and in a 32-bit microcomputer system it has 6 segment registers, so programs developed in this environment can access up to 6 segments at the same time. 32-bit CPUs have two different ways of working: real-mode and protection. In each of these ways, the function of the segment register is different. The relevant provisions are summarized as follows:

Real mode: The first 4 segment registers CS, DS, ES, and SS have exactly the same meaning as the corresponding segment registers in the 16-bit CPU, and the logical address of the memory unit is still the form of "segment value: Offset". To access data in a memory end, the offset of the segment register and the storage unit must be used.

Protection mode: In this way, the situation is much more complex, the loading segment register is no longer a segment value, but a value called "Selector".

1.5 Instruction Pointer Register

The 32-bit CPU expands the instruction pointer to 32 bits, and the lower 16 bits of the EIP,EIP are the same as the IP in the first 16-bit CPU.

The instruction Pointer Eip, IP (instruction Pointer) is the offset in the code snippet that holds the next instruction to be executed. When there is an expected command function, there is no consideration of the presence of the instruction queue. In real mode, since the maximum range for each segment is 64K, the high 16 bits in the EIP are definitely 0, which is equivalent to using only their low 16 bits of IP to reflect the order in which the instructions in the program are executed.

1.6 Flag Register

First, the result of the operation of the flag

1. Carry Flag CF (Carry flag)

The carry flag CF is mainly used to reflect whether the operation produces carry or borrow. If the highest bit of the result of the operation produces a carry or borrow, then the value is 1, otherwise 0. The use of this flag bit is: The number of words (bytes) of the addition and subtraction operations, unsigned size comparison operations, shift operations, the word (bytes) between the shift, specifically to change the CF value of the instructions and so on.

2. Parity Mark bit PF (Parity flag)

The parity flag PF is used to reflect the parity of the number of "1" in the result of the operation, if the number of "1" is even, then the value of PF is 1, otherwise its value is 0. The PF can be used for parity checking, or for generating parity bits. In the process of data transmission, in order to provide the reliability of the transmission, if the use of parity method, you can use this flag.

3. Auxiliary carry sign AF (auxiliary Carry flag)

The value of the secondary carry flag is set to 1 if the following occurs, otherwise its value is 0:

(1) In the word operation, when the low-byte high-byte rounding or borrow occurs;

(2) When the byte operation, the low 4-bit high 4-bit carry or borrow occurs;

For the above 6 operation results of the flag bit, in general programming case, the flag bit CF, ZF, SF, f the use of high frequency, and the use of the flag PF and AF frequency is low.

4.0 flag (Zero flag)

0 symbol ZF is used to reflect whether the result of the operation is 0. If the result of the operation is 0, its value is 1, otherwise its value is 0. You can use this flag bit when judging whether the result of the operation is 0.

5. Symbol SF (sign flag)

The symbolic symbol SF is used to reflect the symbolic bit of the result of the operation, which is the same as the highest bit of the result. In the crisis system, the signed number uses the complement notation, so the SF also reflects the sign of the result of the operation. When the result of the operation is positive, the SF value is 0, otherwise its value is 1.

6. Overflow mark of (Overflow flag)

The overflow callout of is used to reflect whether the result of a signed number plus minus operation overflows. If the result of the operation exceeds the range that can be represented by the current number of operations, it is called overflow, and the value of of is set to 1, otherwise, the value of of is set to 0. "Overflow" and "carry" are two concepts of different meanings.

Second, the status control mark bit

The status control flag bits are used to control CPU operation, and they have to be changed by special instructions.

1. Tracking flag TF (TRAP flag)

When the trace flag TF is set to 1 o'clock, the CPU goes into single step execution, that is, each instruction is executed, resulting in a single-step interrupt request, which is mainly used for debugging the program. There is no specific instruction in the instruction system to change the value of the flag bit TF, but the programmer can use other methods to change its value.

2. Interrupt Allow flag if (interrupt-enable flag)

The interrupt allow flag if is used to determine whether the CPU responds to an interrupt request made by a masked interrupt outside the CPU. However, regardless of the value of the flag, the CPU must respond to an interrupt request from an unshielded interrupt outside the CPU, as well as an interrupt request that is generated internally by the CPU. Specific provisions are as follows:

(1) When if=1, the CPU can respond to interrupt requests made by a masked interrupt outside the CPU;

(2) When if=0, the CPU does not respond to interrupt requests made by a masked interrupt outside the CPU.

The instruction system of the CPU also has special instructions to change the value of the flag bit if.

3. Direction Mark DF (Direction flag)

The direction flag DF is used to determine the direction in which the pointer register adjusts when the string operation instruction executes. In the microcomputer's instruction system summary, also provides the special instruction to change the flag bit DF value.

Three, 32-bit flag register increased flag bit

1.I/O Privilege Flag IOPL (I/O Privilege level)

The I/O privilege flags are represented by two-bit binary, also known as I/O privilege level fields. This field specifies the privilege level that requires the execution of I/O directives. If the current privilege level is less than or equal to the value of IOPL, then the I/O instruction executes, or a protection exception occurs.

2. Nested Task Flags NT (Nested Task)

Nested task Flags NT is used to control the execution of interrupt return instruction Iret. Specific provisions are as follows:

(1) When nt=0, restore EFlags, CS, and EIP with the values stored in the stack, performing a regular interrupt return operation

(2) When Nt=1, interrupt return via task conversion

3. Restart flag RF (Restart flag)

　　Restart flag RF is used to control whether to accept the debug guzheng. Rule: rf=0, "accept" debug failure, otherwise refused. After a successful execution of an instruction, the processor set the RF to 0, and when it accepts a non-debug fault, the processor will set it to 1.

4. Virtual 8086-way flag VM (8086 mode)
　　If the value of this flag is 1, the processor is in the virtual 8086 mode of operation, otherwise, the processor is in a general protection mode of work state.

2 64-bit CPU registers

X86-64cpu in the backward compatibility, but also the main is to inject a new feature, Special: X86-64 has two modes of operation, 32-bit OS can run in the traditional mode, the CPU as a i386 to use, and can run in 64-bit compatibility mode, more amazing, You can run 64-bit applications on a 32-bit OS.

In x86-64, all registers are 64 bits, and the identifiers change, as opposed to 32-bit x86, such as: from the original%EBP to the%RBP. For backwards compatibility, the%EBP is still available, but points to the lower 32 bits of the%RBP.

The change of the X86-64 register is not only reflected in the number of bits, but also in the number of registers. Newly added registers%r8 to%r15. Add x86 original 8, total 16 registers. Register integrated on the CPU, access speed is several orders of magnitude faster than memory, more registers, GCC can be more registers, replace the previous memory stack use, thereby greatly improve performance. The use of registers is generally related to function calls, X86-64 has 16 64-bit registers, namely:%rax,%RBX,%RCX,%RDX,%esi,%edi,%RBP,%RSP,%r8,%r9,%r10,%r11,%r12,%r13,%r14 ,%r15. Among them:

• %rax is used as a function return value.
• %RSP stack pointer register, pointing to the top of the stack
• %RDI,%RSI,%RDX,%RCX,%R8,%R9 is used as a function parameter, corresponding to the 1th parameter, the 2nd parameter ...
• %RBX,%RBP,%R12,%R13,%14,%15 is used as a data store, followed by the callee's rules, simply by using it, and then backing it up before calling the child function in case he is modified
• %r10,%r11 is used as a data store, following the caller's rules of use, simply by saving the original value before use.

　　

Section II excerpt from: 49154509

Dream back----Universal registers for 32-bit CPUs and 64-bit CPUs