Embedded architecture Basics

################### Foundation of the embedded architecture ###############
I. Instruction Set:

1. Data Transmission command --
MVN r0, R2; R0 = ~ R2
Mvns r0, R2; affects CPSR

2. Logic commands --
Add r0, R1, R2; R0 = R1 & r2
ORR r0, R1, R2; R0 = R1 | r2
EOR r0, R1, R2; R0 = R1 ^ r2
Bic r0, R1, R2; R0 = R1 &~ R2

3. Comparison commands-mainly used for loop. When using this command, we need BNE, which is a bit of cyclic test condition;
CMP R1, R2
Tst R1, R2; Set CPSR based on the result of R1 & r2
TEQ R1, R2; according to R1 ^ R2...

4. Arithmetic commands --
ADC r0, R1, R2; R0 = R1 + r2 + carry //??????????????

5. Program Status access command-when you need to modify the content of CPSR/spsr,
First, you need to read its value to a common register -- Mrs r0, CPSR
After modifying some digits, write the data back to the Status Register; -- msr cpsr, R0

6. Single Data Access command --
LDR r0, [R1, #0 xfff]; read the content of memory R1 + 0xfff address to R0.
STR r0, [R1,-R2, LSL #31]; write R0 content to the memory unit of R1-(R2 <31.

7. Multi-Data Access and simulation Stack --
1) hybrid DB = hybrid FD; stack push
Stmfd SP !, {R0-r12, LR}; includes all registers with the return address pressure Stack

2) ldmia = ldmfd; pop
Ldmfd SP !, {R0-r12, PC}; recover all registers including PC

Ii. Exceptions and interruptions
1. Arm mode classification:
######################################## ################
Usr/system | SVC | abort | UNDEF | IRQ | FIQ
R0 R0
R1 R1 r1
R2 r2
R3 R3 r3
R4 r4
R5 R5 R5
R6 R6 R6
R7 R7 r7
R8 R8 R8 r8_fiq
R9 R9 R9
R10 R10 R10
R11 R11 R11
R12 R12 R12

R13 r13_svc r13_abort r13_undef r13_irq
R14 r14_svc r14_abort r14_undef r14_irq

PC

CPSR
Spsr_svc spsr_abort

######################################## ##############

2. CPSR/spsr
1) condition mark
-N = ALU calculation result is negative
-Z = The ALU calculation result is zero.
-C = ALU calculation result carry
-V = ALU computing result Overflow

2) interrupt prohibition bit
-I = 1; turn off IRQ
-F = 1; Disable FIQ
-T:
T = 0; the processor is in the arm state.
T = 1; the processor is in the thumb status.

3. Abnormal and abnormal vector table
1) abnormal vector table-0x18 is IRQ;

2) Priority:
-Reset;
-Data abort;
-FIQ
-IRQ
-Prefetch
-SWI/UNDEF

Exception generation:
1) External exception: reset, Fiq, IRQ
2) Indirect exception: Data termination (memory failure during load and store data access)
3) Direct exception: software interruption, undefined instruction and prefetch instruction

3. mode switching in case of an exception
After an exception occurs
################ What the hardware did before jumping to the abnormal vector table ############### ####
-Copy CPSR to spsr _ <mode>

-Set the appropriate bits in the CPSR to be used in the exception mode.
Clear the thumb bit in CPSR (it is arm status after the exception enters, and it cannot be thumb );
Modify the corresponding mode bit;
Guanzhong disconnection (if a reset or FIQ exception occurs, disable FIQ)

-Map the corresponding mode register;

-Save LR _ <mode> on the PC to return the result;

-Point the PC to an address of the abnormal vector table;

####################### Handling exceptions... #################################
......
...
..
.
.

################ End of exception handling, abnormal Return ##################################
-Recover CPSR from spsr _ <mode>

-Use LR _ <mode> to restore the PC/* pay attention to the impact of the Pipeline */
So, let's discuss how to adjust the return address due to the pipeline in case of various exceptions returned;
-SWI/und: movs PC, r14_swi/und
-FIQ/IRQ/prefetch: subs PC, r14_< mode>, #4
-Dataabr: subs PC, r14_abort, #8

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