Embedded startup 4: s5pv210 irom bl0 startup

Based on the A8 kernel, Samsung s5pv210 is an arm V7 system and is widely used in mobile phone and tablet solutions. There are also many development boards based on s5pv210 chips (such as smart210 and gec210) on the market for learning advanced arm system programming. S5pv210 is basically the same as s5pc11x. Many people think that the two are the same SOC, but they are different in encapsulation. In fact, the two are indeed slightly different. Compared with s5pc11x, s5pv210 does not have the built-in 16msram and power management modules, and the decoding capability is somewhat different. However, from the perspective of software usage, the two have a great similarity in kernel system, integration module, and pin encapsulation. As a result, uboot only supports s5pc11x in terms of naming, but in fact, porting uboot that supports s5pc11x to s5pv210 requires a relatively small workload. The main task is to comment out 16 m of SRAM and PMIC initialization support. Starting from this blog, I will explain in detail the Startup Process of s5pv210. Next I will explain the first phase of irom's bl0 startup.

Embedded startup 2: The General Startup Process of the memory-wide and rich-type embedded system has been described. S5pv210 belongs to this type of system. The plug-in serves as an external storage device, such as SDRAM memory and NAND and SD card. The system and application code are stored as firmware in the external storage device, start the program using the built-in irom of s5pv210 and guide the program to the SDRAM step by step. S5pv210specis s5pv210_um_rev1.1.pdf, in its 29th page ~ The memory ing between irom and Iram is described on page 30. Iram, that is, built-in Ram, has two functions in the boot phase: one is the region where the data variables used during irom running are located, and the other is irom, that is, bl0 directs BL1 from external storage to this region. When irom is started and running, external SDRAM has not been initialized, while Iram is available. Therefore, BL1 must be loaded into Iram to run the task. Why does irom not initialize SDRAM? The reason is that the supported SDRAM specifications are variable, and the initialization by the fixed code is not flexible enough, and the fixed Code usually has a small amount of code, because the more the code, the more bugs, if a bug occurs, the SoC chip will re-mask the film Tapout, which costs millions of RMB at a time. The following figure shows the memory ing:

Irom is 64 K, starting from 0x0000-0000, while Iram is 96 k, in 0xd0020000-0xd0037fff.

The iromspecs of s5pv210is s5pv210_irom_applicationnote_preliminary.pdf, which mainly describes the following content:

1. the startup process, such:

The figure contains a large amount of information and describes most of the knowledge points in the boot guide process.

1) bl0 is located in irom, and the media to be guided is determined by the peripheral pin om level. It can guide the following media: nor, Nand, onenand, SD/MMC, and so on. For example, 0x2 indicates that NAND (page is 2 K byte, 5 command cycles, 8 bit ECC) is started, and 0xc indicates SD/MMC. The OM value can be obtained through the read register 0xe000-0004.

2) based on the OM value, the bl0 in irom selects its fixed-line driver to read the first 16 K code data of the corresponding media to Iram. The boot code is verified. The length of the checksum and BL1 is placed at the Top 16 bytes of 16 K code data. Why length? Because the validation is calculated to determine the length of the content, and the valid code data of BL1 may not be 16 K. The BL1 header information and verification algorithms are as follows:

After BL1 is loaded, bl0 will assign a value to PC 0xd0020010, that is, the real portal of BL1 code should be set to link to 0xd0020010. After compiling the link to survive BL1, you need to use a dedicated tool to calculate the BL1 length and verification code, and fill it in the BL1 header, which is called nand_spl.bin in uboot.

3) The third step in the startup process is just a solution suggestion. In the actual startup module, bl2 is generally large because it includes the boot operating system, it also supports download and other interactive functions in the startup phase. Therefore, bl2 will be larger than the remaining 80 K in Iram. Therefore, when BL1 is executed, it initializes the SDRAM and then directs bl2 to the SDRAM. Therefore, the third step in the figure is not accurate. When BL1 is executed, MMU is disabled. After a temporary page table is created, MMU is enabled and jumps to bl2 for execution.

4) bl2 provides mode commands for interaction with users, which are generally used by R & D personnel for debugging. If a real product does not use this mode, it directly starts to guide the OS to the SDRAM. And jump to the OS to start execution.

5) The General Startup flowchart is as follows:

It can be learned that when the BL1 of the media corresponding to the boot om fails (for example, the media interface has a problem or the verification fails), there is another alternative boot solution, namely 2nd boot, that is USB boot and serial port boot, which will not be expanded here.

2. In addition to boot, irom also initializes some hardware and software environments. The main process includes:

1) disable the watchdog.

2) initialize the Instruction Cache and enable the instruction cache.

3) initialize the stack (Interrupt stack, SVC stack), heap, and exception vector registry in Iram. For example:

Irom is running in SVC mode. The exception vector table is not an abnormal vector table, but is called the exception vector registry. Because the abnormal vector table is at the starting position of irom, that is, the starting position of 0x00000000, as shown below, the environment created by irom can only be interrupted (one exception) registration, that is, register it with 0xd0037418. Support for other exceptions needs to be rebuilt in the startup or OS phase and located in the SDRAM area, and set the base address of the exception vector (by changing the C12-Vector base address register of the coprocessor p15) to point to that region.

_ Start: B Reset
. Word 0x0
. Word 0x0

. Word 0x0

. Word 0x0

. Word 0x0

Ldr pc, _ IRQ
. Word 0x0

4) Fill in the Iram block device read interface area. For example, the first 128 bytes starting with 0xd0037f80 store the copy function address of the block device, such as the read interface address of NAND, SD/MMC. It is used for subsequent use of BL1 and bl2. That is, the BL1 and bl2 codes do not need to implement the read driver function of the external storage device. You only need to call the irom interface. Spec's p14-p18 specifically describes the operational interface addresses and related information for various media devices.

5) Enable the PLL and initialize the system clock.

6) Copy 16 KB BL1 to SRAM.

7) Verify BL1, that is, calculate the BL1 check value, and compare it with the BL1 header check value. If it fails, it will jump to 2nd boot for guidance, if the request succeeds, it is redirected to 0xd0020010 of BL1 for execution.

The uboot Startup Process Based on s5pv210 will be described in detail in the future.

 

Embedded startup 4: s5pv210 irom bl0 startup